1
JEE Main 2021 (Online) 1st September Evening Shift
+4
-1
In the given figure, each diode has a forward bias resistance of 30$$\Omega$$ and infinite resistance in reverse bias. The current I1 will be :

A
3.75 A
B
2.35 A
C
2 A
D
2.73 A
2
JEE Main 2021 (Online) 31st August Evening Shift
+4
-1
If VA and VB are the input voltages (either 5V or 0V) and V0 is the output voltage then the two gates represented in the following circuit (A) and (B) are :-

A
AND and OR Gate
B
OR and NOT Gate
C
NAND and NOR Gate
D
AND and NOT Gate
3
JEE Main 2021 (Online) 31st August Evening Shift
+4
-1
Statement - I :

To get a steady dc output from the pulsating voltage received from a full wave rectifier we can connect a capacitor across the output parallel to the load RL.

Statement - II :

To get a steady dc output from the pulsating voltage received from a full wave rectifier we can connect an inductor in series with RL.

In the light of the above statements, choose the most appropriate answer from the options given below :
A
Statement I is true but Statement II is false
B
Statement I is false but Statement II is true
C
Both Statement I and Statement II are false
D
Both Statement I and Statement II are true
4
JEE Main 2021 (Online) 31st August Morning Shift
+4
-1
In the following logic circuit the sequence of the inputs A, B are (0, 0), (0, 1), (1, 0) and (1, 1). The output Y for this sequence will be :

A
1, 0, 1, 0
B
0, 1, 0, 1
C
1, 1, 1, 0
D
0, 0, 1, 1
EXAM MAP
Medical
NEET