1
GATE ECE 2015 Set 3
MCQ (Single Correct Answer)
+1
-0.3
The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset ($$\overline {{R_d}} $$ input). The counter corresponding to this circuit is GATE ECE 2015 Set 3 Digital Circuits - Sequential Circuits Question 46 English
A
a modulo-5 binary up counter
B
a modulo-6 binary down counter
C
a modulo-5 binary down counter
D
a modulo-6 binary up counter
2
GATE ECE 2014 Set 3
MCQ (Single Correct Answer)
+1
-0.3
The circuit shown in the figure is a GATE ECE 2014 Set 3 Digital Circuits - Sequential Circuits Question 52 English
A
Toggle Flip Flop
B
JK Flip Flop
C
SR Latch
D
Master-Slave D Flip Flop
3
GATE ECE 2014 Set 3
MCQ (Single Correct Answer)
+1
-0.3
Consider the multiplexer based logic circuit shown in the figure. GATE ECE 2014 Set 3 Digital Circuits - Sequential Circuits Question 49 English

Which one of the following Boolean functions is realized by the circuit?

A
F = $$W\overline {{S_1}} \overline {{S_2}} $$
B
F = $$W{S_1}\, + W{S_2}\, + {S_1}{S_2}$$
C
F = $$\overline W + \,{S_1} + {S_2}$$
D
F = $$W \oplus {S_1} \oplus {S_2}$$
4
GATE ECE 2014 Set 1
Numerical
+1
-0
Five JK flip - flops are cascaded to form circuit shown in figure. Clock pulses at a frequency of 1 MHz are applied as shown. The frequency (in kHz) of the waveform at Q3 is ______. GATE ECE 2014 Set 1 Digital Circuits - Sequential Circuits Question 53 English
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