Sequential Circuits ยท Digital Circuits ยท GATE ECE
Start PracticeMarks 1
GATE ECE 2022
for the circuit shown, the clock frequency is f0 and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, ___________.
...
GATE ECE 2022
A state transition diagram with states A, B, and C, and transition probabilities p1, p2, .....,
p7 is shown in the figure (e.g., p1 denotes the prob...
GATE ECE 2018
A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN.
In each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on fo...
GATE ECE 2017 Set 1
Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the cloc...
GATE ECE 2017 Set 1
In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P = Q = "0โ. If the input co...
GATE ECE 2016 Set 2
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor ๐
= 10 ๐ฮฉ and the supply voltage is 5 ๐. The D flip-fl...
GATE ECE 2015 Set 2
A mod-n counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of n is _______.
...
GATE ECE 2015 Set 3
The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset ($$\overline {{R_d}} $$ input).
The counter corresponding to ...
GATE ECE 2014 Set 3
The circuit shown in the figure is a
...
GATE ECE 2014 Set 3
Consider the multiplexer based logic circuit shown in the figure.
Which one of the following Boolean functions is realized by the circuit?...
GATE ECE 2014 Set 1
Five JK flip - flops are cascaded to form circuit shown in figure. Clock pulses at a frequency of 1 MHz are applied as shown. The frequency (in kHz) o...
GATE ECE 2012
Consider the given circuit. In this circuit, the race around
...
GATE ECE 2011
When the output Y in the circuit below is โ1โ, it implies that data has
...
GATE ECE 2010
Assuming that all flip-flops are in reset condition initially, the count sequence
observed at QA in the circuit shown is
...
GATE ECE 2005
The given figure shows a ripple counter using positive edge triggered flip-flops. If the
present state of counter is Q2 Q1 Q0 = 011, then its next st...
GATE ECE 2005
The present output Qn of an edge triggered JK flip-flop is logic 0. If J=1, then
Qn+1
GATE ECE 2004
A master slave flip-flop has the characteristic that
GATE ECE 2004
Choose the correct one from among the alternatives A, B, C, D after matching an
item from Group 1 with the most appropriate item in Group 2.
Group1
P....
GATE ECE 2003
A 0 to 6 counter consist of 3 flip-flops and a combination circuit of 2 input gate(s). The combination circuit consists of
GATE ECE 1998
Figure shows a mod-K counter, Here K is equal to
...
GATE ECE 1997
In a J_K flip-flop, we have J=$$\overline Q $$ and K=1 (see figure). Assuming the flip-flop was intially cleared and then clocked for 6 pulses, the se...
GATE ECE 1995
A switch-tail ring counter is made by using a single D flip-flop. The resulting circuit is a
GATE ECE 1995
An R-S latch is
GATE ECE 1994
Synchronous counters are _____ than the ripple counters.
GATE ECE 1993
A pulse train with a frequency of 1 MHz is counted using a modulo-1024 ripple-counter built with J-K flip flops. For proper operation of the counter, ...
GATE ECE 1992
The initial contents of the 4-bit serial-in-parallel-out, right-shift, Shift Register shown in figure is 0110. After three clock pulses are applied, t...
GATE ECE 1991
A SR FLIP-FLOP can be converted into a T FLIP-FLOP by connecting ___ to Q and ___ to $$\overline Q $$.
GATE ECE 1990
A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 50ns, the maximum clock frequency that can be used is equa...
GATE ECE 1988
The circuit given below is a
...
GATE ECE 1987
A ripple counter using negative edge-triggered D-flip flops is shown in Fig.1. The flip-flops are cleared to '0' by a '0' at the R input. The feedback...
GATE ECE 1987
Choose the correct statements relating to the circuit of figure
...
Marks 2
GATE ECE 2018
In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input
data Din using clock CK. The XOR gate outputs 3.3 volts f...
GATE ECE 2017 Set 1
A 4-bit shift register circuit configured for right-shift operation is $${D_{in}}\, \to \,A,\,A\, \to B,\,B \to C,\,C \to D,$$ is shown. If the presen...
GATE ECE 2017 Set 1
A finite state machine (FSM) is implemented using the D flip-flops A and B and logic gates, as shown in the figure below. The four possible states of ...
GATE ECE 2017 Set 2
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an inpu...
GATE ECE 2016 Set 2
The state transition diagram for a finite state machine with states A, B and C, and binary inputs X, Y and Z, is shown in the figure.
Which one of ...
GATE ECE 2016 Set 2
For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zero
If the clock (Clk) freq...
GATE ECE 2015 Set 2
The figure shows a binary counter with synchronous clear input. With the decoding logic shown,
the counter works as a
...
GATE ECE 2015 Set 3
A three bit pseudo random number generator is shown. Initially the value of output Y = Y2 Y1 Y0 is set to 111. The value of output Y after three clock...
GATE ECE 2015 Set 3
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is o...
GATE ECE 2014 Set 2
In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms
W1, W2, W3 and W4.
...
GATE ECE 2014 Set 2
The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence
generated at Q1 upon application of clock signal i...
GATE ECE 2014 Set 1
The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to
input A of the XOR gate.
Suppose the XOR gate is re...
GATE ECE 2012
The state transition diagram for the logic circuit shown is
...
GATE ECE 2011
The output of a 3-stage Johnson (twisted-ring) counter is fed to a digital-to-analog (D/A) converter as shown in the figure below. Assume all the stat...
GATE ECE 2011
Two D flip-flops are connected as a synchronous counter that goes through the following QB QA sequence $$00 \to 11 \to 01 \to 10 \to 00 \to ......$$ ...
GATE ECE 2009
What are the counting states (Q1, Q2) for the counter shown in the figure below?
...
GATE ECE 2008
For each of the positive edge-triggered J-K flip flop used in the following future, the propagation delay is $$\Delta $$T
Which of the following wav...
GATE ECE 2007
For the circuit shown, the counter state (Q1 Q0) follows the sequence
...
GATE ECE 2007
The following binary values were applied to the X and Y inputs of the NAND latch
shown in the figure in the sequence indicated below: X=0, Y=1; X=0, Y...
GATE ECE 2006
Two D-flip-flops, as shown below, are to be connected as a synchronous counter that goes through the following Q1Q0 sequence $$00 \to 01 \to 11 \to 10...
GATE ECE 2004
In the modulo-6 ripple counter shown in the figure, the output of the 2-input gate is
used to clear the J-K flip-flops. The 2-input gate is
...
GATE ECE 2003
A 4 bit ripple counter and a 4 bit synchronous counter are made using flip-flops having a propagation delay of 10 ns each. If the worst case delay in ...
GATE ECE 2001
The digital block in the figure is realized using two positive edge triggered D flip-flops. Assume that for t < t0, Q1 = Q2 =0. The circuit in the ...
GATE ECE 2000
A sequential circuit using D flip-flop and logic gates is shown in the figure, where X and Y are the inputs and Z is the output. The circuit is
...
GATE ECE 2000
In the figure, the J and K inputs of all the four Flip-Flops are made high. The frequency of the signal at output Y is ...
GATE ECE 1999
The ripple counter shown in the figure works as a
...
GATE ECE 1998
In figure, A = 1 and B = 1. The input B is now replaced by a sequence 101010 ___, the outputs x and y will be
...
Marks 5
GATE ECE 2002
It is required to design a binary mod-5 synchronus counter using AB flip-flops such that the output Q2Q1Q0 changes as $$000 \to 001 \to 010$$ ........
GATE ECE 1999
The circuit diagram of a synchronous counter is shown in the figure. Determine the
sequence of states of the counter assuming that the initial state i...
GATE ECE 1998
The mod-5 counter shown in figure counts through states Q2 Q1 Q0 = 000, 001, 010, 011 and 100.
(a) Will the counter lockout if it happens to be in...
GATE ECE 1997
A sequence generator is shown in figure. The counter status (Q0 Q1 Q3) is intialized to 010 using preset/clear inputs.
The Clock has a period of 50ns ...
GATE ECE 1996
A 4-bit shift register, which shifts 1 bit to the right at every clock pulse, is intialized to values (1000) for (Q0Q1Q2Q3). The D input is derived fr...
GATE ECE 1996
A state machine is required to cycle through the following sequence of states:
One possible implementation of the state machine is shown figure. Spe...
Marks 8
GATE ECE 1992
A new clocked "X-Y" flip-flop is defined with two inputs, X and Y in addition to the clock input. The flip-flop functions as follows:
If XY=00, the fl...
GATE ECE 1988
The circuit shown below uses TTL flip-flops. The flip-flops are triggered at the negative transitions of the clock. It is desired that when M = 1 the ...
GATE ECE 1988
For the circuit shown in the figure below, sketch V0 against time. Assume that all flip-flops are reset to zero before the clock is applied.
...
GATE ECE 1987
A 2-input up/down synchrconous counter using two toggle flip-flops is shown in Fig.1. The counter's sequence is to be controlled by the input M as fol...