Sequential Circuits · Digital Circuits · GATE ECE

Marks 1

The synchronous sequential circuit shown below works at a clock frequency of 1 GHz. The throughput, in Mbits/s, and the latency, in ns, respectively, are

GATE ECE 2023

A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on for 5 seconds and the RED is turned on for 75 seconds. This traffic light has to be implemented using a finite state machine (FSM). The only input to this FSM is a clock of 5 second period. The minimum number of flip-flops required to implement this FSM is _______.

GATE ECE 2018

Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output latch in percentage is ___________.

GATE ECE 2017 Set 1

In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P = Q = "0‟. If the input condition is changed simultaneously to P = Q = "1", the outputs X and Y are

GATE ECE 2017 Set 1

Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor 𝑅 = 10 𝑘Ω and the supply voltage is 5 𝑉. The D flip-flops D₁, D₂, D₃, D₄ and D₅ are initialized with logic values 0, 1, 0,1 and 0, respectively. The clock has a 30% duty cycle.

The average power dissipated (in mW) in resistor R is ______.

GATE ECE 2016 Set 2

The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset ($$\overline {{R_d}} $$ input). The counter corresponding to this circuit is

GATE ECE 2015 Set 3

A mod-n counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of n is _______.

GATE ECE 2015 Set 2

Five JK flip - flops are cascaded to form circuit shown in figure. Clock pulses at a frequency of 1 MHz are applied as shown. The frequency (in kHz) of the waveform at Q₃ is ______.

GATE ECE 2014 Set 1

The circuit shown in the figure is a

GATE ECE 2014 Set 3

Consider the multiplexer based logic circuit shown in the figure.

Which one of the following Boolean functions is realized by the circuit?

GATE ECE 2014 Set 3

Consider the given circuit. In this circuit, the race around

GATE ECE 2012

When the output Y in the circuit below is ‘1’, it implies that data has

GATE ECE 2011

Assuming that all flip-flops are in reset condition initially, the count sequence observed at Q_A in the circuit shown is

GATE ECE 2010

The given figure shows a ripple counter using positive edge triggered flip-flops. If the present state of counter is Q₂ Q₁ Q₀ = 011, then its next state ( Q₂ Q₁ Q₀ ) will be

GATE ECE 2005

The present output Q_n of an edge triggered JK flip-flop is logic 0. If J=1, then Q_n+1

GATE ECE 2005

Choose the correct one from among the alternatives A, B, C, D after matching an item from Group 1 with the most appropriate item in Group 2.

Group1
P. shift register
Q. Counter
R. Decoder

Group2
1. Frequency division
2. Addressing in memory chips
3. Serial to parallel data conversion

GATE ECE 2004

A master slave flip-flop has the characteristic that

GATE ECE 2004

A 0 to 6 counter consist of 3 flip-flops and a combination circuit of 2 input gate(s). The combination circuit consists of

GATE ECE 2003

Figure shows a mod-K counter, Here K is equal to

GATE ECE 1998

In a J_K flip-flop, we have J=$$\overline Q $$ and K=1 (see figure). Assuming the flip-flop was intially cleared and then clocked for 6 pulses, the sequence at the Q output will be

GATE ECE 1997

An R-S latch is

GATE ECE 1995

A switch-tail ring counter is made by using a single D flip-flop. The resulting circuit is a

GATE ECE 1995

Synchronous counters are _____ than the ripple counters.

GATE ECE 1994

A pulse train with a frequency of 1 MHz is counted using a modulo-1024 ripple-counter built with J-K flip flops. For proper operation of the counter, the maximum permissible propagation delay per flip flop stage is ______ n sec.

GATE ECE 1993

The initial contents of the 4-bit serial-in-parallel-out, right-shift, Shift Register shown in figure is 0110. After three clock pulses are applied, the contents of the Shift Register will be

GATE ECE 1992

A SR FLIP-FLOP can be converted into a T FLIP-FLOP by connecting ___ to Q and ___ to $$\overline Q $$.

GATE ECE 1991

A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 50ns, the maximum clock frequency that can be used is equal to:

GATE ECE 1990

The circuit given below is a

GATE ECE 1988

A ripple counter using negative edge-triggered D-flip flops is shown in Fig.1. The flip-flops are cleared to '0' by a '0' at the R input. The feedback logic is to be designed to obtain the count sequence shown in the same figure. The correct feedback logic is:

GATE ECE 1987

Choose the correct statements relating to the circuit of figure

GATE ECE 1987

Marks 2

The sequence of states $(Q_1 Q_0)$ of the given synchronous sequential circuit is ________.

GATE ECE 2024

In a given sequential circuit, initial states are Q$$_1$$ = 1 and Q$$_2$$ = 0. For a clock frequency of 1 MHz, the frequency of signal Q$$_2$$ in kHz, is ___________ (rounded off to the nearest integer).

GATE ECE 2023

for the circuit shown, the clock frequency is f₀ and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, ___________.

GATE ECE 2022

A state transition diagram with states A, B, and C, and transition probabilities p₁, p₂, ....., p₇ is shown in the figure (e.g., p₁ denotes the probability of transition from state A to B). For this state diagram, select the statements which is/are universally true.

GATE ECE 2022

In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data D_in using clock CK. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of $${{\Delta T} \over {{T_{CK}}}}$$ = 0.15, where the parameters $$\Delta T$$ and T_CK are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal.

If the probability of input data bit (D_in) transition in each clock period is 0.3, the average value (in volts, accurate to two decimal places) of the voltage at node X, is _______.

GATE ECE 2018

The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is S₀.

If the input sequence is 10101101001101, starting with the left-most bit, then the number of times 'Out' will be 1 is __________.

GATE ECE 2017 Set 2

A 4-bit shift register circuit configured for right-shift operation is $${D_{in}}\, \to \,A,\,A\, \to B,\,B \to C,\,C \to D,$$ is shown. If the present state of the shift register is ABCD = 1101, the number of clock cycles required to reach the state ABCD = 1111 is

GATE ECE 2017 Set 1

A finite state machine (FSM) is implemented using the D flip-flops A and B and logic gates, as shown in the figure below. The four possible states of the FSM are Q_A Q_B = 00, 01, 10, and 11.

Assume that X_IN is held at a logic level throughout the operation of the FSM. When the FSM is initialized to the state Q_A Q_B = 100 and clocked, after a few clock cycles, it starts cycling through

GATE ECE 2017 Set 1

The state transition diagram for a finite state machine with states A, B and C, and binary inputs X, Y and Z, is shown in the figure.

Which one of the following statements is correct?

GATE ECE 2016 Set 2

For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zero

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a

GATE ECE 2016 Set 2

A three bit pseudo random number generator is shown. Initially the value of output Y = Y₂ Y₁ Y₀ is set to 111. The value of output Y after three clock cycles is

GATE ECE 2015 Set 3

An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing

GATE ECE 2015 Set 3

The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a

GATE ECE 2015 Set 2

The digital logic shown in the figure satisfies the given state diagram when Q₁ is connected to input A of the XOR gate.

Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?

GATE ECE 2014 Set 1

The outputs of the two flip-flops Q₁, Q₂ in the figure shown are initialized to 0, 0. The sequence generated at Q₁ upon application of clock signal is

GATE ECE 2014 Set 2

In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W₁, W₂, W₃ and W₄.

GATE ECE 2014 Set 2

The state transition diagram for the logic circuit shown is

GATE ECE 2012

Two D flip-flops are connected as a synchronous counter that goes through the following Q_B Q_A sequence $$00 \to 11 \to 01 \to 10 \to 00 \to ......$$

GATE ECE 2011

The output of a 3-stage Johnson (twisted-ring) counter is fed to a digital-to-analog (D/A) converter as shown in the figure below. Assume all the states of the counter to be unset initially. The waveform which represents the D/A converter output V_o is

GATE ECE 2011

What are the counting states (Q₁, Q₂) for the counter shown in the figure below?

GATE ECE 2009

For each of the positive edge-triggered J-K flip flop used in the following future, the propagation delay is $$\Delta $$T

Which of the following waveforms correctly represents the output at Q₁?

GATE ECE 2008

The following binary values were applied to the X and Y inputs of the NAND latch shown in the figure in the sequence indicated below: X=0, Y=1; X=0, Y=0; X=1, Y=1. The corresponding stable P, Q outputs will be

GATE ECE 2007

For the circuit shown, the counter state (Q₁ Q₀) follows the sequence

GATE ECE 2007

Two D-flip-flops, as shown below, are to be connected as a synchronous counter that goes through the following Q₁Q₀ sequence $$00 \to 01 \to 11 \to 10 \to 00 \to ......$$
The inputs D₀ and D₁ respectively should be connected as

GATE ECE 2006

In the modulo-6 ripple counter shown in the figure, the output of the 2-input gate is used to clear the J-K flip-flops. The 2-input gate is

GATE ECE 2004

A 4 bit ripple counter and a 4 bit synchronous counter are made using flip-flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then

GATE ECE 2003

The digital block in the figure is realized using two positive edge triggered D flip-flops. Assume that for t < t₀, Q₁ = Q₂ =0. The circuit in the digital block is given by

GATE ECE 2001

A sequential circuit using D flip-flop and logic gates is shown in the figure, where X and Y are the inputs and Z is the output. The circuit is

GATE ECE 2000

In the figure, the J and K inputs of all the four Flip-Flops are made high. The frequency of the signal at output Y is

GATE ECE 2000

The ripple counter shown in the figure works as a

GATE ECE 1999

In figure, A = 1 and B = 1. The input B is now replaced by a sequence 101010 ___, the outputs x and y will be

GATE ECE 1998

Marks 5

It is required to design a binary mod-5 synchronus counter using AB flip-flops such that the output Q₂Q₁Q₀ changes as $$000 \to 001 \to 010$$ ........and so on. The excitation table for the AB flip-flops is given in the table

GATE ECE 2002 Digital Circuits - Sequential Circuits Question 13 English 1

(a) Write down the state table for the mod-5 counter.
(b)Obtain simplified SOP expressions for the inputs A₂, B₂, A₁, B₁, A₀ and B₀ in terms of Q₂, Q₁, Q and their complements.
(c) Hence, complete the circuit diagram for the mod-5 counter given in the figure using minimum number of 2-input NAND-gate only.

GATE ECE 2002

The circuit diagram of a synchronous counter is shown in the figure. Determine the sequence of states of the counter assuming that the initial state is ‘000’. Give your answer in a tabulor form showing the present state Q_A(n), Q_B(n), Q_C(n), J-K inputs ( J_A, K_A, J_B, K_B, J_C, K,) and the next state $${Q_{A\left( {n + 1} \right)}},\,{Q_{B\left( {n + 1} \right)}},{Q_{C\left( {n + 1} \right)}}$$ From the table, determine the modulus of the counter.

GATE ECE 1999

The mod-5 counter shown in figure counts through states Q₂ Q₁ Q₀ = 000, 001, 010, 011 and 100.

GATE ECE 1998 Digital Circuits - Sequential Circuits Question 15 English

(a) Will the counter lockout if it happens to be in any one of the unused states?

(b) Find the maximum rate at which the counter will operate satisfactorily. Assume the propagation delays of flip-flop and AND gate to be t_F and t_A

GATE ECE 1998

A sequence generator is shown in figure. The counter status (Q₀ Q₁ Q₃) is intialized to 010 using preset/clear inputs.
The Clock has a period of 50ns and transitions take place at the rising clock edge.
(a) Give the sequence generated at Q₀ till it repeats.
(b) What is the repetition rate for the generated sequence?

GATE ECE 1997

A 4-bit shift register, which shifts 1 bit to the right at every clock pulse, is intialized to values (1000) for (Q₀Q₁Q₂Q₃). The D input is derived from Q₀, Q₂ and Q₃ through two XOR gates as shown in figure.

GATE ECE 1996 Digital Circuits - Sequential Circuits Question 18 English

(a) Write the 4-bit values (Q₀Q₁Q₂Q₃) after each clock pulse till the pattern (1000) reappears on (Q₀Q₁Q₂Q₃).

(b) To what values should the shift register be intialized so that the pattern (1001) occurs after the first clock pulse?

GATE ECE 1996

A state machine is required to cycle through the following sequence of states:

One possible implementation of the state machine is shown figure. Specify what signals should be applied to each of the multiplexer inputs

GATE ECE 1996

Marks 8

A new clocked "X-Y" flip-flop is defined with two inputs, X and Y in addition to the clock input. The flip-flop functions as follows:

If XY=00, the flip-flop changes stage with each clock pulse.

If XY=01, the flip-flop state Q becomes 1 with the next clock pulse.

If XY=10, the flip-flop state Q becomes 0 with the next clock pulse.

If XY=11, no change of state occurs with the clock pulse.

(a) Write the Truth table for the X-Y flip flop

(b) Write the Excitation table for the X-Y flip flop

(c) It is desired to convert a J-K flip flop into the X-Y flip flop by adding some external gates, if necessary. Draw a circuit to show how you will implement the X-Y flip-flop using a J-K flip-flop.

GATE ECE 1992

The circuit shown below uses TTL flip-flops. The flip-flops are triggered at the negative transitions of the clock. It is desired that when M = 1 the circuit should function as an up-counter (in 8421 BCD) and when M=0, as a down-counter. Design the combinational circuit interposed between the flip-flops so that the circuit works as desired. (i.e. find F as a function of Q,$$\overline Q $$, M, $$\overline M $$).

GATE ECE 1988

For the circuit shown in the figure below, sketch V₀ against time. Assume that all flip-flops are reset to zero before the clock is applied.

GATE ECE 1988

A 2-input up/down synchrconous counter using two toggle flip-flops is shown in Fig.1. The counter's sequence is to be controlled by the input M as follows:
For M=1, sequence of Q₁, Q₀ is ..00, 01, 10, 11, 00, 01.......
For M=0, sequence of Q₁, Q₀ is ..00, 11, 10, 01, 00, 11......

(a)Design the necessary feedback logic for T₁ and T₀.

(b)Realize the feesback logic using inverters and 4-input multiplexers only. Use Q₁ and Q₀ as the control inputs of the multiplexer with Q₁ as the MSB.

GATE ECE 1987