1
GATE ECE 2017 Set 2
MCQ (Single Correct Answer)
+1
-0.3
In a DRAM,
2
GATE ECE 2015 Set 1
Numerical
+1
-0
A 16 Kb (=16,384 bit) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number
of columns). The minimum number of address lines needed for the row decoder is _______.
Your input ____
3
GATE ECE 1996
MCQ (Single Correct Answer)
+1
-0.3
Each cell of a static Random Access Memory Contains
4
GATE ECE 1995
MCQ (Single Correct Answer)
+1
-0.3
The minimum number of MOS transistors required to make a dynamic RAM cell is
Questions Asked from Semiconductor Memories (Marks 1)
Number in Brackets after Paper Indicates No. of Questions
GATE ECE Subjects
Network Theory
Control Systems
Electronic Devices and VLSI
Analog Circuits
Digital Circuits
Microprocessors
Signals and Systems
Representation of Continuous Time Signal Fourier Series Discrete Time Signal Fourier Series Fourier Transform Discrete Time Signal Z Transform Continuous Time Linear Invariant System Transmission of Signal Through Continuous Time LTI Systems Discrete Time Linear Time Invariant Systems Sampling Continuous Time Signal Laplace Transform Discrete Fourier Transform and Fast Fourier Transform Transmission of Signal Through Discrete Time Lti Systems Miscellaneous Fourier Transform
Communications
Electromagnetics
General Aptitude