GATE ECE

Logic Families

Digital Circuits

(Past Years Questions)

Marks 1

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The output (Y) of the circuit shown in the figure is ...
GATE ECE 2014 Set 4
The full forms of the abbreviations TTL and COMS in reference to logic families are
GATE ECE 2009
The transistors used in a portion of the TTL gate shown in figure have β=100. the base-emitter voltage of is 0.7V for a ...
GATE ECE 2005
Both transistors T1 and T2 in figure have a threshold voltage of 1 Volt. The device parameters $${K_1}$$ and $${K_2}$$ ...
GATE ECE 2005
Figure shows the internal schematic of a TTL AND-OR-Invert (AOI) gate. For the inputs shown in Figure, the output Y is ...
GATE ECE 2004
The output of the 74 series of TTL gates is taken from a BJT in
GATE ECE 2003
A Darlington Emitter follower circuit is sometimes used in the output stage of a TTL gate in order to
GATE ECE 1999
Commercially available ECL gates use two ground lines and one negative supply in order to
GATE ECE 1999
The noise margin of a TTL gate is about
GATE ECE 1998
The threshold voltage for each transistor in Fig.2.5, is 2V. For this circuit to work as an inverter, Vi must take the v...
GATE ECE 1998
In standard TTL the 'totem pole' stage refers to
GATE ECE 1997
The inverter 74AL SO4 has the following specifications: $${I_{OH}}{\,_{\max \,}} = \, - $$ 0.4mA, $${I_{OL}}$$ max = ...
GATE ECE 1997
For the NMOS logic gate shown in figure, the logic function implemented is ...
GATE ECE 1997
The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because
GATE ECE 1997
The figure shows the circuit of a gate in the Resistor Transistor Logic (RTL) family. The circuit represents a ...
GATE ECE 1992
The CMOS equivalent of the following n MOS gate (figure) is ________ (draw the circuit ). ...
GATE ECE 1991
In figure, the Boolean expression for the output in terms of inputs A, B and C when the clock ‘CK’ is high, is given by ...
GATE ECE 1991
Among the digital IC-families-ECL, TTL and CMOS:
GATE ECE 1989
A logic family has threshold voltage $${V_T}$$= 2V, minimum guaranteed output high voltage $${V_{OH}}$$= 4V, minimum acc...
GATE ECE 1989
Fill in the blanks of the statements below concerning the following Logic Families: Standard TTL (74XX), Low power TTL(...
GATE ECE 1987

Marks 2

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In the circuit shown below, Q1 has negligible collector-to-emitter saturation voltage and the diode drops negligible vol...
GATE ECE 2013
The logic function implemented by the following circuit at the terminal OUT is ...
GATE ECE 2008
The circuit diagram of a standard TTL NOT gate is shown in the figure. When $${V_i}$$= 2.5V, the modes of operation of ...
GATE ECE 2007
The DTL, TTL, ECL and CMOS families of digital ICs are compared in the following 4 columns ...
GATE ECE 2003
In the output stage of a standard TTL, we have a diode between the emitter of the pull up transistor and the collector o...
GATE ECE 1994
Given that for a logic family, $${V_{OH}}$$ is the minimum output high-level voltage $${V_{OL}}$$ is the minimum outp...
GATE ECE 1987

Marks 8

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Implement the function $$F=\left(\overline A+\overline B\right)\left(\overline C+\overline D\right)$$ using two open col...
GATE ECE 1988

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