Marks 1
Select the correct statement(s) regarding CMOS implementation of NOT gates.
The output (Y) of the circuit shown in the figure is
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The full forms of the abbreviations TTL and COMS in reference to logic families are
Both transistors T1 and T2 in figure have a threshold voltage of 1 Volt. The device parameters $${K_1}$$ and $${K_2}$$ of $${T_1}$$ and $${T_2}$$ are,...
The transistors used in a portion of the TTL gate shown in figure have β=100. the base-emitter voltage of is 0.7V for a transistor in active region a...
Figure shows the internal schematic of a TTL AND-OR-Invert (AOI) gate. For the inputs shown in Figure, the output Y is
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The output of the 74 series of TTL gates is taken from a BJT in
Commercially available ECL gates use two ground lines and one negative supply in order to
A Darlington Emitter follower circuit is sometimes used in the output stage of a TTL gate in order to
The threshold voltage for each transistor in Fig.2.5, is 2V. For this circuit to work as an inverter, Vi must take the values
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The noise margin of a TTL gate is about
In standard TTL the 'totem pole' stage refers to
The inverter 74AL SO4 has the following specifications:
$${I_{OH}}{\,_{\max \,}} = \, - $$ 0.4mA, $${I_{OL}}$$ max = 8mA, $${I_{IH}}$$ max = $$\mu ...
For the NMOS logic gate shown in figure, the logic function implemented is
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The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because
The figure shows the circuit of a gate in the Resistor Transistor Logic (RTL) family. The circuit represents a
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The CMOS equivalent of the following n MOS gate (figure) is ________ (draw the circuit ).
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In figure, the Boolean expression for the output in terms of inputs A, B and C when the clock ‘CK’ is high, is given by _______.
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Among the digital IC-families-ECL, TTL and CMOS:
A logic family has threshold voltage $${V_T}$$= 2V, minimum guaranteed output high voltage $${V_{OH}}$$= 4V, minimum accepted input high voltage $${V_...
Fill in the blanks of the statements below concerning the following Logic Families:
Standard TTL (74XX), Low power TTL(74LXX) Low power schottky TTL(...
Marks 2
In the circuit shown below, Q1 has negligible collector-to-emitter saturation voltage and the diode
drops negligible voltage across it under forward b...
The logic function implemented by the following circuit at the terminal OUT is
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The circuit diagram of a standard TTL NOT gate is shown in the figure. When $${V_i}$$= 2.5V, the modes of operation of the transistors will be:
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The DTL, TTL, ECL and CMOS families of digital ICs are compared in the following 4 columns
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In the output stage of a standard TTL, we have a diode between the emitter of the pull up transistor and the collector of the pull-down transistor. Th...
Given that for a logic family,
$${V_{OH}}$$ is the minimum output high-level voltage
$${V_{OL}}$$ is the minimum output low-level voltage
$${V_{IH...
Marks 8
Implement the function $$F=\left(\overline A+\overline B\right)\left(\overline C+\overline D\right)$$ using two open collector TTL 2-input NAND gates.