1
GATE ECE 2011
MCQ (Single Correct Answer)
+1
-0.3
When the output Y in the circuit below is ‘1’, it implies that data has

GATE ECE 2011 Digital Circuits - Sequential Circuits Question 52 English
A
changed from 0 to 1
B
changed from 1 to 0
C
changed in either direction
D
not changed
2
GATE ECE 2010
MCQ (Single Correct Answer)
+1
-0.3
Assuming that all flip-flops are in reset condition initially, the count sequence observed at QA in the circuit shown is

GATE ECE 2010 Digital Circuits - Sequential Circuits Question 55 English
A
0010111...
B
0001011...
C
0101111...
D
0110100...
3
GATE ECE 2005
MCQ (Single Correct Answer)
+1
-0.3
The given figure shows a ripple counter using positive edge triggered flip-flops. If the present state of counter is Q2 Q1 Q0 = 011, then its next state ( Q2 Q1 Q0 ) will be GATE ECE 2005 Digital Circuits - Sequential Circuits Question 56 English
A
010
B
100
C
111
D
101
4
GATE ECE 2005
MCQ (Single Correct Answer)
+1
-0.3
The present output Qn of an edge triggered JK flip-flop is logic 0. If J=1, then Qn+1
A
can not be determined
B
will be logic 0
C
will be logic 1
D
will race around
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