1
GATE ECE 2011
MCQ (Single Correct Answer)
+1
-0.3
When the output Y in the circuit below is ‘1’, it implies that data has
2
GATE ECE 2010
MCQ (Single Correct Answer)
+1
-0.3
Assuming that all flip-flops are in reset condition initially, the count sequence
observed at QA in the circuit shown is
3
GATE ECE 2005
MCQ (Single Correct Answer)
+1
-0.3
The present output Qn of an edge triggered JK flip-flop is logic 0. If J=1, then
Qn+1
4
GATE ECE 2005
MCQ (Single Correct Answer)
+1
-0.3
The given figure shows a ripple counter using positive edge triggered flip-flops. If the
present state of counter is Q2 Q1 Q0 = 011, then its next state ( Q2 Q1 Q0 ) will be
GATE ECE Subjects
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Control Systems
Engineering Mathematics
Analog Circuits
Network Theory
Electromagnetics
Electronic Devices and VLSI
Digital Circuits
Microprocessors
Signals and Systems
Discrete Time Signal Fourier Series Fourier Transform Continuous Time Signal Laplace Transform Fourier Transform Discrete Fourier Transform and Fast Fourier Transform Representation of Continuous Time Signal Fourier Series Discrete Time Linear Time Invariant Systems Transmission of Signal Through Continuous Time LTI Systems Transmission of Signal Through Discrete Time Lti Systems Miscellaneous Continuous Time Linear Invariant System Discrete Time Signal Z Transform Sampling
Communications
General Aptitude