FET and MOSFET · Analog Circuits · GATE ECE

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Marks 1

1

In the circuit below, assume that the long channel NMOS transistor is biased in saturation. The small signal trans-conductance of the transistor is $g_m$. Neglect body effect, channel length modulation, and intrinsic device capacitances. The small signal input impedance $Z_{in}(j\omega)$ is _______

GATE ECE 2024 Analog Circuits - FET and MOSFET Question 3 English
GATE ECE 2024
2

In the circuit shown below, $$V_1$$ and $$V_2$$ are bias voltages. Based on input and output impedances, the circuit behaves as a

GATE ECE 2023 Analog Circuits - FET and MOSFET Question 4 English

GATE ECE 2023
3

Consider the CMOS circuit shown in the figure (substrates are connected to their respective sources). The gate width (W) to gate length (L) ratios $$\left( {{W \over L}} \right)$$ of the transistors are as shown. Both the transistors have the same gate oxide capacitance per unit area. For the pMOSFET, the threshold voltage is $$-$$1 V and the mobility of holes is $$40{{c{m^2}} \over {V.s}}$$. For the nMOSFET, the threshold voltage is 1 V and the mobility of electrons is $$300{{c{m^2}} \over {V.s}}$$. The steady state output voltage V0 is ___________.

GATE ECE 2022 Analog Circuits - FET and MOSFET Question 5 English

GATE ECE 2022
4

The ideal long channel nMOSFET and pMOSFET devices shown in the circuits have threshold voltages of 1 V and $$-$$1 V, respectively. The MOSFET substrates are connected to their respectively sources. Ignore leakage currents and assume that the capacitors are initially discharged. For the applied voltages as shown, the steady state voltages are ____________.

GATE ECE 2022 Analog Circuits - FET and MOSFET Question 8 English

GATE ECE 2022
5
In the MOSFET amplifier of the figure the signal output V1 and V2 obey the relationship GATE ECE 1998 Analog Circuits - FET and MOSFET Question 23 English
GATE ECE 1998
6
An n-channel JFET has IDSS = 1 mA and Vp = -5 V. Its maximum transconductance is ______
GATE ECE 1995
7
The transit time of a current carriers through the channel of an FET decides its ____________characteristics.
GATE ECE 1994

Marks 2

1

In the circuit shown below, the transistors $M_1$ and $M_2$ are biased in saturation. Their small signal transconductances are $g_{m1}$ and $g_{m2}$ respectively. Neglect body effect, channel length modulation and intrinsic device capacitances.

GATE ECE 2024 Analog Circuits - FET and MOSFET Question 2 English

Assuming that capacitor $C_i$ is a short circuit for AC analysis, the exact magnitude of small signal voltage gain $\left| \frac{v_{out}}{v_{in}} \right|$ is ______.

GATE ECE 2024
2

An NMOS transistor operating in the linear region has $I_{D}$ of 5 $\mu$A at $V_{DS}$ of 0.1 V. Keeping $V_{GS}$ constant, the $V_{DS}$ is increased to 1.5 V.

Given that $\mu_{n}C_{ox} \frac{W}{L}$ = 50 $\mu$A/$V^2$, the transconductance at the new operating point (in $\mu$A/V, rounded off to two decimal places) is ______.

GATE ECE 2024
3

Consider an ideal long channel nMOSFET (enhancement-mode) with gate length 10 $$\mu$$m and width 100 $$\mu$$m. The product of electron mobility ($$\mu$$n) and oxide capacitance per unit area (Cox) is $$\mu$$nCox = 1 mA/V2. The threshold voltage of the transistor is 1 V. For a gate-to-source voltage VGS = [2 $$-$$ sin(2t)] V and drain-to source voltage VDS = 1 V (substrate connected to the source), the maximum value of the drain-to-source current is ___________.

GATE ECE 2022
4

Consider the circuit shown with an ideal long channel nMOSFET (enhancement mode, substrate is connected to the source). The transistor is appropriately biased in the saturation region with VGG and VDD such that it acts as a linear amplifier. vi is the small-signal ac input voltage. vA and vB represent the small-signal voltages at the nodes A and B, respectively. The value of $${{{v_A}} \over {{v_B}}}$$ is __________ (rounded off to one decimal place).

GATE ECE 2022 Analog Circuits - FET and MOSFET Question 6 English

GATE ECE 2022
5
The ac schematic of an NMOS common-source stage is shown in the figure below, where part of the biasing circuits has been omitted for simplicity. For the n -channel MOSFET M, the transconductance gm = 1 mA/V, and body effect and channel length modulation effect are to be neglected. The lower cutoff frequency in Hz of the circuit is approximately at GATE ECE 2013 Analog Circuits - FET and MOSFET Question 13 English
GATE ECE 2013
6
An n-channel depletion MOSFET has following two points on its ID - VGS curve:

(i)VGS = 0 at Id = 12 mA and
(ii)VGS = -6 Volts at Zo =$$\infty $$

Which of the following Q-points will give the highest transconductance gain for small signals?

GATE ECE 2006
7
Given
$${r_d} = 20K\Omega ,\,\,{I_{DSS}}\, = \,10mA,\,\,{V_P} = - 8V$$ GATE ECE 2005 Analog Circuits - FET and MOSFET Question 18 English

Zi and Zo of the circuit are respectively

GATE ECE 2005
8
Given
$${r_d} = 20K\Omega ,\,\,{I_{DSS}}\, = \,10mA,\,\,{V_P} = - 8V$$ GATE ECE 2005 Analog Circuits - FET and MOSFET Question 16 English

Transconductance in milli-Siemens (mS) and voltage gain of the amplifier are respectively.

GATE ECE 2005
9
Given
$${r_d} = 20K\Omega ,\,\,{I_{DSS}}\, = \,10mA,\,\,{V_P} = - 8V$$ GATE ECE 2005 Analog Circuits - FET and MOSFET Question 17 English

ID and VDS under DC conditions are respectively

GATE ECE 2005
10
For an n-channel MOSFET and its transfer curve shown in the figure, the threshold voltage is GATE ECE 2005 Analog Circuits - FET and MOSFET Question 15 English 1 GATE ECE 2005 Analog Circuits - FET and MOSFET Question 15 English 2
GATE ECE 2005
11
The action of a JFET in its equivalent circuit can be best represented as a
GATE ECE 2003
12
Consider the following statements in connection with the CMOS inverter in the Figure. Where both the MOSFETS are of enhancement type and both have a threshold voltage of 2V.

Statement 1: T1 conducts when Vi $$ \ge \,2\,V$$.
Statement 2: T1 is always in saturation when $${V_0}\, = \,0\,V$$.

Which of the following is correct?

GATE ECE 2002 Analog Circuits - FET and MOSFET Question 20 English
GATE ECE 2002
13
An n-channel JFET has a pinch-off voltage of Vp = -5V. VDS(max) = 20V and gm = 2mA/V. The minimum 'ON' resistance is achieved in the JFET for
GATE ECE 1992
14
The JFET in the circuit shown in fig. has an IDSS = 10mA and Vp = -5V. The value of the resistance Rs for a drain current IDS = 6.4mA is (select the Nearest value). GATE ECE 1992 Analog Circuits - FET and MOSFET Question 21 English
GATE ECE 1992

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