IC Basics and MOSFET · Electronic Devices and VLSI · GATE ECE

Marks 1

For a MOS capacitor, $$\mathrm{V_{fb}}$$ and $$\mathrm{V_{t}}$$ are the flat-band voltage and the threshold voltage, respectively. The variation of the depletion width ($$\mathrm{W_{dep}}$$) for varying gate voltage ($$\mathrm{V_{g}}$$) is best represented by

GATE ECE 2023

For the circuit shown in the figure, P and Q are the inputs and Y is the output.

The logic implemented by the circuit is

GATE ECE 2017 Set 2

Consider an n-channel MOSFET having width W, length L, electron mobility in the channel $$\mu_n$$ and oxide capacitance per unit area $$C_{ox}$$. If gate-to-source voltage V_GS=0.7 V, drain-to source voltage V_DS=0.1V, $$\left(\mu_nC_{ox}\right)\;=\;100\;\mu A/V^2$$, threshold voltage V_TH=0.3 V and (W/L) = 50, then the transconductance g_m (in mA/V) is ___________.

GATE ECE 2017 Set 2

An n-channel enhancement mode MOSFET is biased at V_GS > V_TH and V_DS > (V_GS - V_TH), where V_GS is the gate-to-source voltage, V_DS is the drain-to-source voltage and V_TH is the threshold voltage. Considering channel length modulation effect to be significant, the MOSFET behaves as a

GATE ECE 2017 Set 2

Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET):

P: As channel length reduces, OFF-state current increases.
Q:As channel length reduces, output resistance increases.
R: As channel length reduces, threshold voltage remains constant.
S: As channel length reduces, ON current increases.

Which of the above statements are INCORRECT?

GATE ECE 2016 Set 1

What is the voltage V_out in the following circuit?

GATE ECE 2016 Set 1

The figure shows the band diagram of a Metal Oxide Semiconductor (MOS). The surface region of this MOS is in

GATE ECE 2016 Set 3

Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for worst case charge and discharge times for driving a load capacitor C. This design is to be converted to that of a NOR circuit in the same technology, so that its worst case charge and discharge times while driving the same capacitor are similar. The channel lengths of all transistors are to be kept unchanged. Which one of the following statements is correct?

GATE ECE 2016 Set 2

A long-channel NMOS transistor is biased in the linear region with V_DS = 50 mV and is used as a resistance. Which one of the following statements is NOT correct?

GATE ECE 2016 Set 2

Which one of the following processes is preferred to from the gate dielectric (SiO₂) of MOSFETs?

GATE ECE 2015 Set 3

In the ac equivalent circuit shown in the figure, if i_n is the input current and R_F is very large, the type of feedback

GATE ECE 2014 Set 1

If fixed positive charges are present in the gate oxide of an n-channel enhancement type MOSFET, it will lead to

GATE ECE 2014 Set 1

In the following circuit employing pass transistor logic, all NMOS transistors are identical with a threshold voltage of 1 V. Ignoring the body-effect, the output voltages at P, Q and R are,

GATE ECE 2014 Set 1

In MOSFET fabrication, the channel length is defined during the process of

GATE ECE 2014 Set 3

In CMOS technology, shallow P-well or N-well regions can be formed using

GATE ECE 2014 Set 2

In a MOSFET operating in the saturation region, the channel length modulation effect causes

GATE ECE 2013

In IC technology, dry oxidation (using dry oxygen) as compared to wet oxidation (using steam or water vapor) produces

GATE ECE 2013

In the circuit shown

GATE ECE 2012

In the circuit shown below, for the MOS transistors, $$\mu_nC_{ox}\;=\;100\;\mu A/V^2$$ and the threshold voltage V_T = 1 V. The voltage V_x at the source of the upper transistor is

GATE ECE 2011

The drain current of a MOSFET in saturation is given by $$I_D\;=\;K\left(V_{GS}\;-V_T\right)^2$$ where 'K' is a constant. The magnitude of the transconductance g_m is

GATE ECE 2008

A silicon wafer has 100 mm of oxide on it and is inserted in a furnace at a temperature above 1000ºC for further oxidation in dry oxygen. The oxidation rate

GATE ECE 2008

A MOS capacitor made using p-type substrate is in the accumulation mode. The dominant charge in the channel is due to the presence of

GATE ECE 2005

Consider the following statements S1 and S2.

S1: The threshold voltage (V_T) of a MOS capacitor decreases with increase in gate oxide thickness

S2: The threshold voltage (V_T) of a MOS capacitor decreases with increase in substrate doping concentration.

Which one of the following is correct?

GATE ECE 2004

The threshold voltage of an n-channel MOSFET can be increased by

GATE ECE 1994

Marks 2

Consider a MOS capacitor made with p-type silicon. It has an oxide thickness of 100 nm, a fixed positive oxide charge of $10^{-8}$ C/cm² at the oxide-silicon interface, and a metal work function of 4.6 eV. Assume that the relative permittivity of the oxide is 4 and the absolute permittivity of free space is $8.85 × 10^{-14}$ F/cm. If the flatband voltage is 0 V, the work function of the p-type silicon (in eV, rounded off to two decimal places) is ______.

GATE ECE 2024

In the circuit below, the voltage V$$_{\mathrm{L}}$$ is _____________ V (rounded off to two decimal places).

GATE ECE 2023

Two n-channel MOSFETs, T1 and T2, are identical in all respects except that the width of T2 is double of T1. Both the transistor are biased in the saturation region of operation, but the gate overdrive voltage (V_GS - V_TH) of T2 is double that of T1, where V_GS and V_TH are the gate-to-source voltage and threshold voltage of the transistors, respectively. If the drain current and transconductance of T1 are I_D1 and g_m1 respectively ; the corresponding values of these two parameters for T2 are

GATE ECE 2017 Set 2

Assuming that transistor M₁ and M₂ are identical and have a threshold voltage of 1V, the state of transistors M₁ and M₂ are respectively

GATE ECE 2017 Set 2

A MOS capacitor is fabricated on p-type Si (silicon) where the metal work function is 4.1 eV and electron affinity of Si is 4.0 eV, E_c - E_F = 0.9 eV; where E_c and E_F are conduction band minimum and the Fermi energy levels of Si, respectively. Oxide$${\varepsilon _r} = \,\,3.9,\,\,\,{\varepsilon _{0\,\,}}=\,8.85 \times {10^{ - 14}}$$ F/cm, oxide thickness $${t_{ox}} = 0.1\,\mu m$$ and electronic charge q = $$1.6 \times {10^{ - 19}}$$ C. If the measured flat band voltage of the capacitor is –1V, then the magnitude of the fixed charge at the oxide semiconductor interface, in nC/cm², is __________.

GATE ECE 2017 Set 2

For the circuit shown, assume that the NMOS transistor is in saturation. Its threshold voltage V_tn = 1 V and its trans-conductance parameter $${\mu _n}{C_{ox}}\left( {{W \over L}} \right) = 1m{\rm A}/{V^2}.$$ Neglect channel length modulation and body bias effects. Under these conditions the drain current I_D in mA is______.

GATE ECE 2017 Set 1

Consider an n-channel metal oxide semiconductor field effect transistor (MOSFET) with a gate-to-source voltage of 1.8 V. Assume that $${W \over L} = 4,{\mu _{\rm N}}{C_{ox}} = 70 \times {10^{ - 6}}{\rm A}{V^{ - 2}}$$ , the threshold voltage is 0.3V, and the channel length modulation parameter is 0.09 V^-1, In the saturation region, the drain conductance (in micro siemens) is__________.

GATE ECE 2016 Set 1

Figures $${\rm I}$$ and $${\rm I}{\rm I}$$ show two MOS capacitor of unit area. The capacitor in Figure I has insulator materials X (of thickness t₁ = 1 nm and dielectric constant $${\varepsilon _1}$$ = 4) and Y (of thickness t₂ =3 nm and dielectric constant $${\varepsilon _2}$$ = 200). The capacitor in Figure $${\rm I}{\rm I}$$ has only insulator material X of thickness t_eq. If the capacitors are of equal capacitance, then the value of t_eq (in nm) is ______

GATE ECE 2016 Set 3

In the circuit shown in the figure, the channel length modulation of all transistors is non-zero $$\left( {\lambda \ne 0} \right)$$. Also all transistors operate in saturation and have negligible body effect. The ac small signal voltage gain $$\left( {{V_0}/{V_{in}}} \right)$$ of the circuit is

GATE ECE 2016 Set 3

In the circuit shown in the figure, transistor M1 is in saturation and has transconductance g_m = 0.01 siemens. Ignoring internal parasitic capacitances and assuming the channel length modulation $$\lambda $$ to be zero, the small signal input pole frequency (in kHz) is _____

GATE ECE 2016 Set 3

Consider a long-channel NMOS transistor with source and body connected together. Assume that the electron mobility is independent of V_GS and V_DS. Given,
g_m = 0.5$$\mu {\rm A}/V$$ for V_DS = 50 m V and V_GS = 2V,
g_d = $$8\mu {\rm A}/V$$ for V_GS = 2 V and V_DS = 0 V,
Where g_m =$${{\partial {{\rm I}_D}} \over {\partial {V_{GS}}}}\,\,and\,\,{g_d}\,\, = \,{{\partial {{\rm I}_D}} \over {\partial {V_{DS}}}}$$

The threshold voltage (in volts) of the transistor is

GATE ECE 2016 Set 2

A voltage V_G is applied across a MOS capacitor with metal gate and p-type silicon substrate at T=300 K. The inversion carrier density (in number of carriers per unit area) for V_G = 0.8 V is $$2\,\, \times \,\,{10^{11}}\,\,\,\,\,\,c{m^{ - 2}}$$ . For $${V_G}\,\, = \,\,1.3\,\,V,$$ the inversion carrier density is $$4\,\,\, \times \,\,\,{10^{11}}\,\,\,\,c{m^{ - 2}}.$$ What is the value of the inversion carrier density for V_G = 1.8 V?

GATE ECE 2016 Set 2

In the circuit shown, both the enhancement mode NMOS transistors have the following characteristics: k_n = $${\mu _n}{C_{ox}}(W/L) = 1m{\rm A}/{V^2}$$ ; V_TN = 1V. Asuume that the channel length modulation parameter $$\lambda $$ is zero and body is shorted to source. The minimum supply voltage V_DD (in volts) needed to ensure that transistor M₁ operates in saturation mode of operation is _____

GATE ECE 2015 Set 3

The current in an enhancement mode NMOS transistor biased in saturation mode was measured to be 1 mA at a drain-source voltage of 5 V. When the drain-source voltage was increased to 6 V while keeping gate-source voltage same, the drain current increased to 1.02 mA. Assume that drain to source saturation voltage is much smaller than the applied drain-source voltage. The channel length modulation p[arameter $$\lambda $$ (in V^-1) is _______

GATE ECE 2015 Set 3

In a MOS capacitor with an oxide layer thickness of 10 nm, the maximum depletion layer thickness is 100 nm. The permittivities of the semiconductor and the oxide layer are $${\varepsilon _s}$$ and $${\varepsilon _{os}}$$ respectively. Asuuming $${\varepsilon _s}/{\varepsilon _{ox}} = 3$$ , the ratio of the maximum capacitance to the minimum capacitance of this MOS capacitor is________

GATE ECE 2015 Set 2

A MOSFET in saturation has a drain current of 1 mA for V_DS =0.5V. If the channel length modulation coefficient is 0.05 V^-1, the output resistance (in k$$\Omega $$) of the MOSFET is______

GATE ECE 2015 Set 1

For the NMOSFET in the circuit shown, in the threshold voltage is V_th, where V_th>0. The source voltage V_ss is varied from 0 to V_DD. Neglecting the channel length modulation, the drain current I_D as a function of V_ss is represented by

GATE ECE 2015 Set 1

A depletion type N -channel MOSFET is biased in its linear region for use as a voltage controlled resistor. Assume threshold voltage V_TH = -0.5 V, V_GS = 2.0 V, V_DS = 5 V, W/L=100, C_OX=10^-8 F/cm² and $${\mu _n}$$ = 800 cm²/V-s. The value of the resistance of the voltage controlled resistor (in $$\Omega $$ ) is _____.

GATE ECE 2014 Set 1

The slope of the I_D vs. V_GS curve of an n-channel MOSFET in linear region is 10^-3$${\Omega ^{ - 1}}$$ at V_DS = 0.1V. For the same device, neglecting channel length modulation, the slope of the $$\sqrt {{{\rm I}_D}} $$ vs. V _GS curve (in $$\sqrt A /V$$ ) under saturation region is approximately ______.

GATE ECE 2014 Set 3

An ideal MOS capacitor has boron doping concentration of 10¹⁵ cm^-3 in the substrate. When a gate voltage is applied, a depletion region of width 0.5 $$\mu m$$ is formed with a surface (channel) potential of 0.2V. Given that $${\varepsilon _0} = 80854 \times {10^{ - 14}}F/cm$$ and the relative permittivities of silicon and silicon dioxide are 12 and 4, respectively, the peak electric field (in V/ $$\mu m$$ ) in the oxide region is ______

GATE ECE 2014 Set 3

For the MOSFET M₁ shown in the figure, assume W/L =2, V_DD = 2.0 V, $$\mu n$$ C_OX = 100$$\mu {\rm A}/{V^2}$$ and V_TH =0.5 V. The transistor M₁ switches from saturation region to linear regionm when V_in(in Volts) is _____

GATE ECE 2014 Set 3

For the MOSFETs shown in the figure, the threshold voltage |V_t| = 2V and
K=$${1 \over 2}\mu {C_{OX}}\left( {{W \over L}} \right) = 0.1mA/{V^2}$$ . The value of I_D (in mA) is _______

GATE ECE 2014 Set 2

For the n-channel MOS transistor shown in the figure, the threshold voltage V_Th is 0.8V. Neglect channel length modulation effects. When the drain voltage V_D = 1.6 V, the drain current I_D was found to be 0.5 mA.

GATE ECE 2014 Set 2

The small-signal resistance (i.e., $${{d{V_B}} \over {d{I_D}}}$$ ) in $$k\Omega $$ offered by the n-channel MOSFET M shown in the figure below, at bias point of V_B = 2V is (device data for M: device transconductance parameter

k_N = $${\mu _n}{C_{ox}^{'}}$$ (W/L)= 40$$\mu {\rm A}/{V^2},$$ threshold voltage V_TN=1V, and neglect body effect and channel length modulation effects)