GATE ECE
Electronic Devices and VLSI
IC Basics and MOSFET
Previous Years Questions

## Marks 1

An n-channel enhancement mode MOSFET is biased at VGS > VTH and VDS > (VGS - VTH), where VGS is the gate-to-source voltage, VDS is the drain-to-...
Consider an n-channel MOSFET having width W, length L, electron mobility in the channel $$\mu_n$$ and oxide capacitance per unit area $$C_{ox}$$. If g...
For the circuit shown in the figure, P and Q are the inputs and Y is the output. The logic implemented by the circuit is ...
The figure shows the band diagram of a Metal Oxide Semiconductor (MOS). The surface region of this MOS is in ...
A long-channel NMOS transistor is biased in the linear region with VDS = 50 mV and is used as a resistance. Which one of the following statements is ...
Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for worst case charge and discharge times for driving a load capac...
Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET): P: As channel length reduces, OFF-state current in...
What is the voltage Vout in the following circuit? ...
Which one of the following processes is preferred to from the gate dielectric (SiO2) of MOSFETs?
In MOSFET fabrication, the channel length is defined during the process of
In CMOS technology, shallow P-well or N-well regions can be formed using
If fixed positive charges are present in the gate oxide of an n-channel enhancement type MOSFET, it will lead to
In the ac equivalent circuit shown in the figure, if in is the input current and RF is very large, the type of feedback ...
In the following circuit employing pass transistor logic, all NMOS transistors are identical with a threshold voltage of 1 V. Ignoring the body-effect...
In IC technology, dry oxidation (using dry oxygen) as compared to wet oxidation (using steam or water vapor) produces
In a MOSFET operating in the saturation region, the channel length modulation effect causes
In the circuit shown ...
In the circuit shown below, for the MOS transistors, $$\mu_nC_{ox}\;=\;100\;\mu A/V^2$$ and the threshold voltage VT = 1 V. The voltage Vx at the sou...
A silicon wafer has 100 mm of oxide on it and is inserted in a furnace at a temperature above 1000ºC for further oxidation in dry oxygen. The oxidatio...
The drain current of a MOSFET in saturation is given by $$I_D\;=\;K\left(V_{GS}\;-V_T\right)^2$$ where 'K' is a constant. The magnitude of the transco...
A MOS capacitor made using p-type substrate is in the accumulation mode. The dominant charge in the channel is due to the presence of
Consider the following statements S1 and S2. S1: The threshold voltage (VT) of a MOS capacitor decreases with increase in gate oxide thickness S2: The...
The threshold voltage of an n-channel MOSFET can be increased by

## Marks 2

Assuming that transistor M1 and M2 are identical and have a threshold voltage of 1V, the state of transistors M1 and M2 are respectively ...
Two n-channel MOSFETs, T1 and T2, are identical in all respects except that the width of T2 is double of T1. Both the transistor are biased in the sat...
A MOS capacitor is fabricated on p-type Si (silicon) where the metal work function is 4.1 eV and electron affinity of Si is 4.0 eV, Ec - EF = 0.9 eV...
For the circuit shown, assume that the NMOS transistor is in saturation. Its threshold voltage Vtn = 1 V and its trans-conductance parameter $${\mu ... Figures$${\rm I}$$and$${\rm I}{\rm I}$$show two MOS capacitor of unit area. The capacitor in Figure I has insulator materials X (of thickness t... In the circuit shown in the figure, transistor M1 is in saturation and has transconductance gm = 0.01 siemens. Ignoring internal parasitic capacitance... In the circuit shown in the figure, the channel length modulation of all transistors is non-zero$$\left( {\lambda \ne 0} \right)$$. Also all transis... A voltage VG is applied across a MOS capacitor with metal gate and p-type silicon substrate at T=300 K. The inversion carrier density (in number of ca... Consider a long-channel NMOS transistor with source and body connected together. Assume that the electron mobility is independent of VGS and VDS. Give... Consider an n-channel metal oxide semiconductor field effect transistor (MOSFET) with a gate-to-source voltage of 1.8 V. Assume that$${W \over L} =...
In the circuit shown, both the enhancement mode NMOS transistors have the following characteristics: kn = $${\mu _n}{C_{ox}}(W/L) = 1m{\rm A}/{V^2}$$ ...
The current in an enhancement mode NMOS transistor biased in saturation mode was measured to be 1 mA at a drain-source voltage of 5 V. When the drain-...
In a MOS capacitor with an oxide layer thickness of 10 nm, the maximum depletion layer thickness is 100 nm. The permittivities of the semiconductor an...
A MOSFET in saturation has a drain current of 1 mA for VDS =0.5V. If the channel length modulation coefficient is 0.05 V-1, the output resistance (i...
For the NMOSFET in the circuit shown, in the threshold voltage is Vth, where Vth>0. The source voltage Vss is varied from 0 to VDD. Neglecting th...
An ideal MOS capacitor has boron doping concentration of 1015 cm-3 in the substrate. When a gate voltage is applied, a depletion region of width 0.5 \$...
The slope of the ID vs. VGS curve of an n-channel MOSFET in linear region is 10-3$${\Omega ^{ - 1}}$$ at VDS = 0.1V. For the same device, neglecting ...
For the MOSFET M1 shown in the figure, assume W/L =2, VDD = 2.0 V, $$\mu n$$ COX = 100$$\mu {\rm A}/{V^2}$$ and VTH =0.5 V. The transistor M1 switches...
For the n-channel MOS transistor shown in the figure, the threshold voltage VTh is 0.8V. Neglect channel length modulation effects. When the drain vol...
For the MOSFETs shown in the figure, the threshold voltage |Vt| = 2V and K=$${1 \over 2}\mu {C_{OX}}\left( {{W \over L}} \right) = 0.1mA/{V^2}$$ . The...
A depletion type N -channel MOSFET is biased in its linear region for use as a voltage controlled resistor. Assume threshold voltage VTH = -0.5 V, VGS...
The small-signal resistance (i.e., $${{d{V_B}} \over {d{I_D}}}$$ ) in $$k\Omega$$ offered by the n-channel MOSFET M shown in the figure below, at bia...
The source of a silicon (ni = 1010 per cm3) n - channel MOS transistor has an aewa of 1 sq $$\mu m$$ and a depth of 1 $$\mu m$$ . If the dopant densit...
In the three dimensional view of a silicon n-channel MOS transistor shown below, $$\delta = 20$$ nm. The transistor is of width 1 $$\mu m$$. The depl...
In the three dimensional view of a silicon n-channel MOS transistor shown below, $$\delta = 20$$ nm. The transistor is of width 1 $$\mu m$$. The depl...
In the CMOS circuit shown, electron and hole mobilities are equal, and M1 and M2 are equally sized. The device M1 is in the linear region if ...
Consider the CMOS circuit shown, where the gate voltage of the n-MOSFET is increased from zero, while the gate voltage of the p-MOSFET is kept constan...
Consider the CMOS circuit shown, where the gate voltage of the n-MOSFET is increased from zero, while the gate voltage of the p-MOSFET is kept constan...
Two identical NMOS transistors M1 and M2 are connected as shown below. Vbias is chosen so that both transistors are in saturation. The equivalent gm o...
For the circuit shown in the following figure, transistors M1 and M2 are identical NMOS transistors. Assume that M2 is in saturation and the output is...
The measured transconductance gm of an NMOS transistor operating in the linear region is plotted against the gate voltage VG at constant drain voltage...
In the CMOS inverter circuit shown, if the transconductance parameters of the NMOS and PMOS transistors are Kn = Kp = μnCOX$$\frac{W_n}{L_n}$$ = μpCO...
An n-channel depletion MOSFET has following two points on its ID − VGS curve: (i) VGS = 0 at ID = 12 mA and (ii) VGS = - 6 Volts at ID = 0 Which of th...
The drain of an n-channel MOSFET is shorted to the gate so that VGS = VDS. The threshold voltage (VT) of MOSFET is 1 V. If the drain current (ID) is 1...
When the gate-to-source voltage (VGS) of a MOSFET with threshold voltage of 400 mV, working in saturation is 900 mV, the drain current is observed to ...
For an n-channel enhancement type MOSFET, if the source is connected at a higher potential than that of the bulk (i.e. VSB > 0), the threshold volt...
If P is Passivation, Q is n-well implant, R is metallization and S is source/drain diffusion, then the order in which they are carried out in a standa...
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