GATE ECE

Pin Details of 8085 and Interfacing With 8085

Microprocessors

(Past Years Questions)

Marks 1

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In the circuit shown, the device connected to Y5 can have address in the range ...
GATE ECE 2010
In the circuit shown, the device connected to Y5 can have address in the range ...
GATE ECE 2010
The number of hardware interrupts (which require an external signal to interrupt) present in an 8085 microprocessor are
GATE ECE 2000
In the 8085 microprocessor, the RST6 instruction transfers the program execution to the following location
GATE ECE 2000
If $$CS\;=\overline{A_{15}}\;A_{14}\;A_{13}$$ is used as the chip select logic of a 4K RAM in an 8085 system, then its ...
GATE ECE 1999
An I/O processor control the flow of information between
GATE ECE 1998
In an 8085$$\mu$$P system, the RST instruction will cause an interrupt
GATE ECE 1997
The decoding circuit shown below has been used to generate the active low chip select signal for a microprocessor periph...
GATE ECE 1997
In a microprocessor, when a CPU is interrupted, it
GATE ECE 1995
In a microcomputer, wait states are used to
GATE ECE 1993
In an 8085 microprocessor system with memory mapped I/O,
GATE ECE 1992
For a microprocessor system using I/O-mapped I/O the following statement(s) is NOT true
GATE ECE 1988
A microprocessor with a 16-bit address bus is used in a linear memory selection configuration (i.e. Address bus lines ar...
GATE ECE 1988
A 8bit $$\mu $$p has 16bit address bus. A 1KB memory chip is interfaced to processor as shown ib figure. The address ra...
GATE ECE 1988

Marks 2

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An 8 Kbyte ROM with an active low Chip Select input CS is to be used in an 8085 microprocessor based system. The ROM sho...
GATE ECE 2016 Set 2
For the 8085 microprocessor, the interfacing circuit to input 8-bit digital data (DI0 – DI7) from an external device is ...
GATE ECE 2014 Set 2
There are four chips each of 1024 bytes connected to a 16 bit address bus as shown in the figure below. RAMs 1,2,3 and 4...
GATE ECE 2013
An I/O peripheral device shown in figure (b) below is to be interfaced to an 8085 microprocessor. To select the I/O devi...
GATE ECE 2006
What memory address range is NOT represented by chip 1 and chip 2 in figure? A0 to A15 in this figure are the address li...
GATE ECE 2005
The 8255 Programmable Peripheral Interface is used as described below. I. An A/D converter is interfaced to a microproce...
GATE ECE 2004
An 8085 microprocessor based system uses a 4K × 8-bit RAM whose starting address is AA00H. The address of the last byte ...
GATE ECE 2001

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