1
GATE ECE 1991
Fill in the Blanks
+1
-0
A SR FLIP-FLOP can be converted into a T FLIP-FLOP by connecting ___ to Q and ___ to $$\overline Q $$.
2
GATE ECE 1990
MCQ (Single Correct Answer)
+1
-0.3
A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 50ns, the maximum clock frequency that can be used is equal to:
3
GATE ECE 1988
MCQ (Single Correct Answer)
+1
-0.3
The circuit given below is a
4
GATE ECE 1987
MCQ (Single Correct Answer)
+1
-0.3
A ripple counter using negative edge-triggered D-flip flops is shown in Fig.1. The flip-flops are cleared to '0' by a '0' at the R input. The feedback logic is to be designed to obtain the count sequence shown in the same figure. The correct feedback logic is:
GATE ECE Subjects
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Network Theory
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Analog Circuits
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Discrete Fourier Transform and Fast Fourier Transform Discrete Time Signal Fourier Series Fourier Transform Continuous Time Signal Laplace Transform Fourier Transform Representation of Continuous Time Signal Fourier Series Transmission of Signal Through Continuous Time LTI Systems Miscellaneous Sampling Continuous Time Linear Invariant System Discrete Time Linear Time Invariant Systems Discrete Time Signal Z Transform Transmission of Signal Through Discrete Time Lti Systems
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General Aptitude