1
GATE ECE 2016 Set 2
Numerical
+1
-0
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor 𝑅 = 10 𝑘Ω and the supply voltage is 5 𝑉. The D flip-flops D1, D2, D3, D4 and D5 are initialized with logic values 0, 1, 0,1 and 0, respectively. The clock has a 30% duty cycle. GATE ECE 2016 Set 2 Digital Circuits - Sequential Circuits Question 48 English

The average power dissipated (in mW) in resistor R is ______.

Your input ____
2
GATE ECE 2015 Set 2
Numerical
+1
-0
A mod-n counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of n is _______. GATE ECE 2015 Set 2 Digital Circuits - Sequential Circuits Question 47 English
Your input ____
3
GATE ECE 2015 Set 3
MCQ (Single Correct Answer)
+1
-0.3
The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset ($$\overline {{R_d}} $$ input). The counter corresponding to this circuit is GATE ECE 2015 Set 3 Digital Circuits - Sequential Circuits Question 46 English
A
a modulo-5 binary up counter
B
a modulo-6 binary down counter
C
a modulo-5 binary down counter
D
a modulo-6 binary up counter
4
GATE ECE 2014 Set 3
MCQ (Single Correct Answer)
+1
-0.3
The circuit shown in the figure is a GATE ECE 2014 Set 3 Digital Circuits - Sequential Circuits Question 52 English
A
Toggle Flip Flop
B
JK Flip Flop
C
SR Latch
D
Master-Slave D Flip Flop
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