1
GATE ECE 1993
Numerical
+1
-0
A pulse train with a frequency of 1 MHz is counted using a modulo-1024 ripple-counter built with J-K flip flops. For proper operation of the counter, the maximum permissible propagation delay per flip flop stage is ______ n sec.
Your input ____
2
GATE ECE 1992
MCQ (Single Correct Answer)
+1
-0.3
The initial contents of the 4-bit serial-in-parallel-out, right-shift, Shift Register shown in figure is 0110. After three clock pulses are applied, the contents of the Shift Register will be GATE ECE 1992 Digital Circuits - Sequential Circuits Question 67 English
A
0000
B
0101
C
1010
D
1111
3
GATE ECE 1991
Fill in the Blanks
+1
-0
A SR FLIP-FLOP can be converted into a T FLIP-FLOP by connecting ___ to Q and ___ to $$\overline Q $$.
4
GATE ECE 1990
MCQ (Single Correct Answer)
+1
-0.3
A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 50ns, the maximum clock frequency that can be used is equal to:
A
20 MHz
B
10 MHz
C
5 MHz
D
4 MHz
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