1
GATE ECE 1990
+1
-0.3
A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 50ns, the maximum clock frequency that can be used is equal to:
A
20 MHz
B
10 MHz
C
5 MHz
D
4 MHz
2
GATE ECE 1988
+1
-0.3
The circuit given below is a
A
J-K Flip-flop
B
Johnson's counter
C
R-S latch
D
None of above
3
GATE ECE 1987
+1
-0.3
A ripple counter using negative edge-triggered D-flip flops is shown in Fig.1. The flip-flops are cleared to '0' by a '0' at the R input. The feedback logic is to be designed to obtain the count sequence shown in the same figure. The correct feedback logic is:
A
$$F\, = \overline {{Q_2}{Q_1}\overline {{Q_0}} }$$
B
$$F\, = \,{Q_2}\,\overline {{Q_1}} \overline {{Q_0}}$$
C
$$F\, = \,\overline {{Q_2}} \overline {{Q_1}} {Q_0}$$
D
$$F\, = \,\overline {{Q_2}} \overline {{Q_1}} \overline {{Q_0}}$$
4
GATE ECE 1987
+1
-0.3
Choose the correct statements relating to the circuit of figure
A
For Vi = -2V, P=0
B
For Vi = +3V, P=0
C
For Vi = 0V, P=0 always
D
For Vi = 0V, P can be either 0 or 1.
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