# Combinational Circuits Β· Digital Circuits Β· GATE ECE

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## Marks 1

GATE ECE 2022
Consider the 2-bit multiplexer (MUX) shown in the figure. For OUTPUT to be the XOR of C and D, the values for A0, A1, A2 and A3 are ___________. ...
GATE ECE 2017 Set 2
Consider the circuit shown in the figure. The Boolean expression F implemented by the circuit is ...
GATE ECE 2016 Set 2
A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are the bits to be added while πΆin is the input carry and οΏ½...
GATE ECE 2014 Set 2
In a half-subtractor circuit with X and Y as inputs, the Borrow (M) and Difference (N = X - Y) are given by
GATE ECE 2012
The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the ...
GATE ECE 2011
The logic function implemented by the circuit below is (ground implies a logic "0" ...
GATE ECE 2005
The Boolean function f implemented in the figure using two input multiplexers is ...
GATE ECE 2003
With out any additional circuitry, an 8:1 MUX can be used to obtain
GATE ECE 1997
A 2-bit binary multiplier can be implemented using
GATE ECE 1995
The output of the circuit shown in figure is equal to ...
GATE ECE 1992
The logic realized by the circuit shown in figure is ...
GATE ECE 1990
The minimum function that can detect a "divisible by 3" 8421 BCD code digit (representation is D8 D4 D2 D1) is given by:...

## Marks 2

GATE ECE 2018
A four-variable Boolean function is realized using 4 $$\times$$ 1 multiplexers as shown in the figure. The minimized expression for F(U, V, W, X) i...
GATE ECE 2017 Set 2
A programmable logic array (PLA) is shown in the figure. The Boolean function F implemented is ...
GATE ECE 2017 Set 2
Figure I shows a 4-bits ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The propagation delay of...
GATE ECE 2016 Set 3
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are 2 ns, 1.5 ns and 1 ns, respectively. If all the inputs P,...
GATE ECE 2016 Set 1
The functionality implemented by the circuit below is ...
GATE ECE 2016 Set 1
Identify the circuit below. ...
GATE ECE 2015 Set 2
A 1-to-8 demultiplexer with data input D$$_{in}$$ , address inputs S$$_{0}$$, S$$_{1}$$, S$$_{2}$$ (with S$$_{0}$$ as the LSB) and $${\overline Y _0}... GATE ECE 2014 Set 4 A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns an... GATE ECE 2014 Set 4 An 8-to-1 multiplexer is used to implement a logical function Y as shown in the figure. The output Y is given by ... GATE ECE 2014 Set 3 In the circuit shown, ππ and ππ are MSBs of the control inputs. The output πΉπΉ is given by ... GATE ECE 2014 Set 3 If X and Y are inputs and the Difference (D = X β Y) and the Borrow (B) are the outputs, which one of the following diagrams implements a half-subtra... GATE ECE 2010 The Boolean function realized by the logic circuit shown is ... GATE ECE 2009 What are the minimum number of 2-to 1 multiplexers required to generate a 2-input AND gate and a 2-input EX-OR gate? GATE ECE 2008 For the circuit shown in the following figure$${I_0}$$-$${I_3}$$are inputs to the 4:1 multiplexer R(MSB) and S are control bits. tHE OUTPUT Zcan b... GATE ECE 2007 In the following circuit, X is given by ... GATE ECE 2004 The minimum number of 2 to 1 multiplexers required to realize a 4 to 1 mutliplexer is GATE ECE 2003 The circuit shown in figure converts ... GATE ECE 2003 The circuit shown in figure has 4 boxes each described by inputs P, Q, R and outputs Y, Z with Y =$$\,P \oplus \,Q\, \oplus \,R$$z=$$RQ + \overli...
GATE ECE 2001
In the TTL circuit in Figure 2.11, $${S_0}$$ to $${S_0}$$ are select lines and $${X_7}$$ and $${X_0}$$are input lines. $${S_0}$$ and $${X_0}$$ are LSB...
GATE ECE 1999
For a binary half-sub-tractor having two inputs A and B, the correct set of logical expressions for the outputs D (=A minus B) and X (=borrow) are

## Marks 5

GATE ECE 2002
The inputs to a digital circuit shown in Figure 9(a) are the external signals A, B and C. ( $$\overline A \,\overline B \,and\,\overline {C\,}$$ an...

## Marks 8

GATE ECE 1987
The circuit diagram of a 2 bit A to D converter is shown in figure below. The combinational logic is to be disigned to provide a natural binary repres...

## Marks 10

GATE ECE 1995
A ROM is to be used to implement the Boolean functions given below: $${F_1}$$$$(A,\,B,\,C,\,D) = ABCD + \bar A\,\overline B \,\bar C\,\bar D$$ $${F_... GATE ECE 1994 A Boolean function, F , given as sum of product (SOP) terms as F=$$\sum {} $$m(3,4,5,6) with A,B, and C as inputs. The function, F, can be expreeed o... GATE ECE 1993 Signals A,B,C,D and$$\overline D $$are available. Using a single 8 - to - 1 multiplexer and no other gate, implement the Boolean function.$$f(A,B,C...
GATE ECE 1989
A chemical reactor has three sensors indicating the following conditions:- (1) Pressure (P) is low or high' (2) Temperature (T) is low or high' and ...
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