1
GATE ECE 1992
MCQ (Single Correct Answer)
+1
-0.3
The initial contents of the 4-bit serial-in-parallel-out, right-shift, Shift Register shown in figure is 0110. After three clock pulses are applied, the contents of the Shift Register will be
2
GATE ECE 1991
Fill in the Blanks
+1
-0
A SR FLIP-FLOP can be converted into a T FLIP-FLOP by connecting ___ to Q and ___ to $$\overline Q $$.
3
GATE ECE 1990
MCQ (Single Correct Answer)
+1
-0.3
A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 50ns, the maximum clock frequency that can be used is equal to:
4
GATE ECE 1988
MCQ (Single Correct Answer)
+1
-0.3
The circuit given below is a
Questions Asked from Sequential Circuits (Marks 1)
Number in Brackets after Paper Indicates No. of Questions
GATE ECE 2023 (1)
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GATE ECE 2010 (1)
GATE ECE 2005 (2)
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GATE ECE 2003 (1)
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GATE ECE 1997 (1)
GATE ECE 1995 (2)
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GATE ECE 1992 (1)
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GATE ECE 1987 (2)
GATE ECE Subjects
Network Theory
Control Systems
Electronic Devices and VLSI
Analog Circuits
Digital Circuits
Microprocessors
Signals and Systems
Representation of Continuous Time Signal Fourier Series Discrete Time Signal Fourier Series Fourier Transform Discrete Time Signal Z Transform Continuous Time Linear Invariant System Transmission of Signal Through Continuous Time LTI Systems Discrete Time Linear Time Invariant Systems Sampling Continuous Time Signal Laplace Transform Discrete Fourier Transform and Fast Fourier Transform Transmission of Signal Through Discrete Time Lti Systems Miscellaneous Fourier Transform
Communications
Electromagnetics
General Aptitude