GATE ECE

Semiconductor Memories

Digital Circuits

(Past Years Questions)

Marks 1

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In a DRAM,
GATE ECE 2017 Set 2
A 16 Kb (=16,384 bit) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the n...
GATE ECE 2015 Set 1
Each cell of a static Random Access Memory Contains
GATE ECE 1996
The minimum number of MOS transistors required to make a dynamic RAM cell is
GATE ECE 1995
A PLA can be used
GATE ECE 1994
A dynamic RAM consists of
GATE ECE 1994
Choose the correct satatement(s) from the following:
GATE ECE 1992

Marks 2

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A 2 $$ \times $$ 2 ROM array is built with the help of diodes as shown in the circuit below. Here W0 and W1 are signals ...
GATE ECE 2018
If WL is the Word Line and BL the Bit Line, an SRAM cell is shown in
GATE ECE 2014 Set 3
In the circuit shown in Figure, A is a parallel in, parallel-out 4-bit register, which loads at the rising edge of the c...
GATE ECE 2003
If the input X$$_3$$, X$$_2$$, X$$_1$$, X$$_0$$ to the ROM in figure 2.12 are 8-4-2-1 BCD numbers, then the outpus are ...
GATE ECE 2002

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