Logic Gates · Digital Circuits · GATE ECE

Marks 1

For the circuit shown below, the propagation delay of each NAND gate is 1 ns. The critical path delay, in ns, is __________ (rounded off to the nearest integer).

GATE ECE 2023

The output of the combinational circuit given below is

GATE ECE 2016 Set 1

The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is

GATE ECE 2016 Set 3

In the circuit shown, diodes $${D_1}$$ ,$${D_2}$$ and $${D_3}$$ are ideal, and the inputs $${E_1}$$ , $${E_2}$$ and $${E_3}$$ are “0 V” for logic ‘0’ and “10 V” for logic ‘1’. What logic gate does the circuit represent?

GATE ECE 2015 Set 3

In the figure shown, the output ܻ is required to be ܻ Y=AB+ $$\overline C $$$$\overline D $$. The gates G1 and G2 must be, respectively,

GATE ECE 2015 Set 2

In the circuit shown in the figure, if C = 0, the expression for Y is

GATE ECE 2014 Set 4

A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON and also can be turned OFF by any one of the switches irrespective of the state of the other switch. The logic of switching of the bulb resembles.

GATE ECE 2013

The output Y in the circuit below is always ‘1’ when

GATE ECE 2011

Match the logic gates in column A with their equivalents in column B.

GATE ECE 2010

For the output F to be 1 in the logic circuit shown, the input combination should be

GATE ECE 2010

If the input to the digital circuit (in the figure) consisting of a cascade of 20 XOR-gates is X then the output Y is equal to

GATE ECE 2002

For the ring oscillator shown in the figure, the propagation delay of each inverter is 100 pico sec. What is the fundamental frequency of the oscillator output?

GATE ECE 2001

For the logic circuit shown in Figure, the required input condition (A, B, C) to make the output (X)=1.

GATE ECE 2000

The output of the logic gate in figure is

GATE ECE 1997

The minimum number of NAND gates required to implement the Boolean function $$A + A\overline B $$ $$ + A\overline B C$$ is equal to

GATE ECE 1995

A ring oscillator consisting of 5 inverters is running at a frequency of 1.0 MH$$_z$$. The progagation delay per gate is ______

GATE ECE 1994

For the logic circuit shown in Figure, the output is equal to

GATE ECE 1993

Boolean expression for the output of XNOR (equivalence) logic gate with inputs A and B is

GATE ECE 1993

Indicate which of the following logic gates can be used to realize all possible combinational Logic functions:

GATE ECE 1989

For the circuit shown below the output Fis given by

GATE ECE 1988

The minimum number of 2-input NAND gates required to implement the Boolean function Z=A$$\overline {B\,} $$C, assuming that A, B and C are available, is

GATE ECE 1988

The Boolean function A+BC is a reduced form of

GATE ECE 1988

For the identity AB+$$\overline A $$ C + BC= AB + $$\overline A $$ C, The dual form is

GATE ECE 1988

Minimum number of 2-input NAND gates required to implement the function, f=($$\overline X $$+$$\overline Y $$)(Z+W) is

GATE ECE 1988

Marks 2

Consider a Boolean gate (D) where the output Y is related to the inputs A and b as, Y = A + $$\overline B $$, where + denotes logical OR operation. The Boolean inputs '0' and '1' are also available separately. Using instances of only D gates and inputs '0' and '1', ___________ (select the correct options).

GATE ECE 2022

The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes are intentionally shorted to implement “wired logic”. Such shorted nodes will be HIGH only if the outputs of all the gates whose outputs are shorted are HIGH.

The number of distinct values of X₃X₂X₁X₀ (out of the 16 possible values) that give 𝑌 = 1 is _______.

GATE ECE 2018

A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown.

GATE ECE 2015 Set 3 Digital Circuits - Logic Gates Question 8 English 1

Which one of the following statesments is TRUE?

GATE ECE 2015 Set 3

All the logic gates shown in the figure have a propagation delay of 20 ns. Let A = C = 0 and B = 1 until time t = 0. At t = 0, all the inputs flip (i.e., A = C = 1 and B = 0) and remain in that state. For t > 0, output Z = 1 for a duration (in ns) of ______________.

GATE ECE 2015 Set 1

A 3-input majority gate is defined by the logic function M (a,b,c) = ab+bc+ca. Which one of the following gates is represented by the function M$$\left( {\overline {M\left( {a,b,c} \right),} M\left( {a,b,\overline c } \right),c} \right)?$$

GATE ECE 2015 Set 1

The output F in the digital logic circuit shown in the figure is

GATE ECE 2014 Set 1

Which of the follwing Boolean expression correctly represents the relation between P, Q, R and M₁?

GATE ECE 2008

The gates G₁ and G₂ in figure have propagation delays of 10nsec and 20nsec respectively. If the input V_i makes an abrupt change from logic 0 to 1 at time t = t₀, then the output waveform V₀ is

GATE ECE 2002

In the figure the LED

GATE ECE 2001

For the logic circuit shown in the figure, the simplified Boolean expression for the output Y is

GATE ECE 2000

Marks 5

For the digital block shown in Figure. 2(a), the output Y=f(S₃,S₂,S₁,S₀) where S₃ is MSB and S₀ is LSB. Y is given in terms of minterms as $$Y\, = \,\sum m\left( {1,5,6,7,11,12,13,15} \right)$$ and its complements $$\overline Y \, = \,\sum m\left( {0,2,3,4,8,9,10,14} \right)$$.

GATE ECE 2001 Digital Circuits - Logic Gates Question 6 English 1

(a) Enter the logical values in the given Karnaugh map [figure2(b)] for the output Y.
(b) Write down the expression for Y in sum-of products from using minimum number of terms.
(c) Draw the circuit for the digital logic boxes using four 2-input NAND gates only for each of the boxes.

GATE ECE 2001

The operating conditions (ON = 1, OFF = 0) of three pumps (x,y,z) are to be monitored. x = 1 implies that pump X is on. It is required that the indicator (LED) on the panel should glow when a majority of the pumps fail.

(a) Enter the logical values in the K-map in the format shown in figure 3(a). Derive the minimal Boolean sum-of-products expression whose output is zero when a majority of the pumps fail.
(b) The above expression is implemented using logic gates, and point P is the output of this circuit, as shown in figure 3(b). P is at 0 V when a majority of the pumps fails and is at 5 V otherwise. Design a circuit to drive the LED using this output. The current through the LED should be 10 mA and the voltage drop across it is 1V. Assume that P can source or sink 10 mA and a 5 V supply is available.

GATE ECE 2000

The truth table for the output Y in terms of three inputs A, B and C are given in table. Draw a logic circuit realization using only NOR gates.

GATE ECE 1993

Marks 8

A combinational circuit has three inputs A, B and C and an output F. F is true only for the following input combinations?

A is false and B is true
A is false and C is true
A, B and C are all false
A, B and C are all true.

(a)Write the truth table for F. use the convention, true = 1 and false = 0.
(b)Write the simplified expression for F as a Sum of Products.
(c) Write the simplified expression for F as a product of Sums.
(d) Draw a logic circuit implementation of F using the minimum number of 2 input NAND gates only.

GATE ECE 1992