1
GATE ECE 2017 Set 1
Numerical
+1
-0
Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output latch in percentage is ___________.
2
GATE ECE 2017 Set 1
+1
-0.3
In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P = Q = "0‟. If the input condition is changed simultaneously to P = Q = "1", the outputs X and Y are
A
X = '1', Y = '1'
B
either X = '1', Y = '0' or X = '0', Y = '1'
C
either X = '1', Y = '1' or X = '0', Y = '0'
D
X = '0', Y = '0'
3
GATE ECE 2016 Set 2
Numerical
+1
-0
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor 𝑅 = 10 𝑘Ω and the supply voltage is 5 𝑉. The D flip-flops D1, D2, D3, D4 and D5 are initialized with logic values 0, 1, 0,1 and 0, respectively. The clock has a 30% duty cycle.

The average power dissipated (in mW) in resistor R is ______.

4
GATE ECE 2015 Set 2
Numerical
+1
-0
A mod-n counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of n is _______.