1
GATE ECE 1987
MCQ (Single Correct Answer)
+1
-0.3
A ripple counter using negative edge-triggered D-flip flops is shown in Fig.1. The flip-flops are cleared to '0' by a '0' at the R input. The feedback logic is to be designed to obtain the count sequence shown in the same figure. The correct feedback logic is:
2
GATE ECE 1987
MCQ (Single Correct Answer)
+1
-0.3
Choose the correct statements relating to the circuit of figure
Questions Asked from Sequential Circuits (Marks 1)
Number in Brackets after Paper Indicates No. of Questions
GATE ECE 2023 (1)
GATE ECE 2018 (1)
GATE ECE 2017 Set 1 (2)
GATE ECE 2016 Set 2 (1)
GATE ECE 2015 Set 2 (1)
GATE ECE 2015 Set 3 (1)
GATE ECE 2014 Set 3 (2)
GATE ECE 2014 Set 1 (1)
GATE ECE 2012 (1)
GATE ECE 2011 (1)
GATE ECE 2010 (1)
GATE ECE 2005 (2)
GATE ECE 2004 (2)
GATE ECE 2003 (1)
GATE ECE 1998 (1)
GATE ECE 1997 (1)
GATE ECE 1995 (2)
GATE ECE 1994 (1)
GATE ECE 1993 (1)
GATE ECE 1992 (1)
GATE ECE 1991 (1)
GATE ECE 1990 (1)
GATE ECE 1988 (1)
GATE ECE 1987 (2)
GATE ECE Subjects
Network Theory
Control Systems
Electronic Devices and VLSI
Analog Circuits
Digital Circuits
Microprocessors
Signals and Systems
Representation of Continuous Time Signal Fourier Series Discrete Time Signal Fourier Series Fourier Transform Discrete Time Signal Z Transform Continuous Time Linear Invariant System Transmission of Signal Through Continuous Time LTI Systems Discrete Time Linear Time Invariant Systems Sampling Continuous Time Signal Laplace Transform Discrete Fourier Transform and Fast Fourier Transform Transmission of Signal Through Discrete Time Lti Systems Miscellaneous Fourier Transform
Communications
Electromagnetics
General Aptitude