GATE ECE 2015 Set 3 | Sequential Circuits Question 18 | Digital Circuits

GATE ECE 2015 Set 3

MCQ (Single Correct Answer)

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An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing GATE ECE 2015 Set 3 Digital Circuits - Sequential Circuits Question 26 English

GATE ECE 2015 Set 3 Digital Circuits - Sequential Circuits Question 26 English

NOR gates to NAND gates

inverts to buffers

NOR gates to NAND gates and inverters to buffers

5 V to ground

GATE ECE 2015 Set 2

MCQ (Single Correct Answer)

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The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a GATE ECE 2015 Set 2 Digital Circuits - Sequential Circuits Question 28 English

GATE ECE 2015 Set 2 Digital Circuits - Sequential Circuits Question 28 English

mod - 2 counter

mod - 4 counter

mod - 5 counter

mod - 6 counter

GATE ECE 2014 Set 1

MCQ (Single Correct Answer)

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The digital logic shown in the figure satisfies the given state diagram when Q₁ is connected to input A of the XOR gate. GATE ECE 2014 Set 1 Digital Circuits - Sequential Circuits Question 33 English

GATE ECE 2014 Set 1 Digital Circuits - Sequential Circuits Question 33 English

Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?

Input A is connected to $${\overline Q _2}$$

Input A is connected to $${Q_2}$$

Input A is connected to $${\overline Q _1}$$ and S is complemented

Input A is connected to $${\overline Q _1}$$

GATE ECE 2014 Set 2

MCQ (Single Correct Answer)

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In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W₁, W₂, W₃ and W₄. GATE ECE 2014 Set 2 Digital Circuits - Sequential Circuits Question 32 English 1