1
GATE ECE 2015 Set 3
MCQ (Single Correct Answer)
+2
-0.6
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing GATE ECE 2015 Set 3 Digital Circuits - Sequential Circuits Question 26 English
A
NOR gates to NAND gates
B
inverts to buffers
C
NOR gates to NAND gates and inverters to buffers
D
5 V to ground
2
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a GATE ECE 2015 Set 2 Digital Circuits - Sequential Circuits Question 28 English
A
mod - 2 counter
B
mod - 4 counter
C
mod - 5 counter
D
mod - 6 counter
3
GATE ECE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence generated at Q1 upon application of clock signal is GATE ECE 2014 Set 2 Digital Circuits - Sequential Circuits Question 31 English
A
01110
B
01010
C
00110
D
01100
4
GATE ECE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W1, W2, W3 and W4. GATE ECE 2014 Set 2 Digital Circuits - Sequential Circuits Question 32 English 1 GATE ECE 2014 Set 2 Digital Circuits - Sequential Circuits Question 32 English 2
A
W1
B
W2
C
W3
D
W4
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