1
GATE ECE 2016 Set 2
MCQ (Single Correct Answer)
+2
-0.6
For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zero GATE ECE 2016 Set 2 Digital Circuits - Sequential Circuits Question 22 English

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a

A
mod-5 counter
B
mod-6 counter
C
mod-7 counter
D
mod-8 counter
2
GATE ECE 2015 Set 3
MCQ (Single Correct Answer)
+2
-0.6
A three bit pseudo random number generator is shown. Initially the value of output Y = Y2 Y1 Y0 is set to 111. The value of output Y after three clock cycles is GATE ECE 2015 Set 3 Digital Circuits - Sequential Circuits Question 25 English
A
000
B
001
C
010
D
100
3
GATE ECE 2015 Set 3
MCQ (Single Correct Answer)
+2
-0.6
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing GATE ECE 2015 Set 3 Digital Circuits - Sequential Circuits Question 24 English
A
NOR gates to NAND gates
B
inverts to buffers
C
NOR gates to NAND gates and inverters to buffers
D
5 V to ground
4
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a GATE ECE 2015 Set 2 Digital Circuits - Sequential Circuits Question 26 English
A
mod - 2 counter
B
mod - 4 counter
C
mod - 5 counter
D
mod - 6 counter
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