What are the counting states (Q₁, Q₂) for the counter shown in the figure below?

For each of the positive edge-triggered J-K flip flop used in the following future, the propagation delay is $$\Delta $$T

Which of the following waveforms correctly represents the output at Q₁?

The following binary values were applied to the X and Y inputs of the NAND latch shown in the figure in the sequence indicated below: X=0, Y=1; X=0, Y=0; X=1, Y=1. The corresponding stable P, Q outputs will be

For the circuit shown, the counter state (Q₁ Q₀) follows the sequence