1

GATE ECE 2018

Numerical

+2

-0.67

In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input
data D

If the probability of input data bit (D

_{in}using clock CK. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of $${{\Delta T} \over {{T_{CK}}}}$$ = 0.15, where the parameters $$\Delta T$$ and T_{CK}are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal.If the probability of input data bit (D

_{in}) transition in each clock period is 0.3, the average value (in volts, accurate to two decimal places) of the voltage at node X, is _______.Your input ____

2

GATE ECE 2017 Set 2

Numerical

+2

-0

The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is S

_{0}.If the input sequence is 10101101001101, starting with the left-most bit, then the number of times 'Out' will be 1 is __________.

Your input ____

3

GATE ECE 2017 Set 1

Numerical

+2

-0

A 4-bit shift register circuit configured for right-shift operation is $${D_{in}}\, \to \,A,\,A\, \to B,\,B \to C,\,C \to D,$$ is shown. If the present state of the shift register is ABCD = 1101, the number of clock cycles required to reach the state ABCD = 1111 is

Your input ____

4

GATE ECE 2017 Set 1

MCQ (Single Correct Answer)

+2

-0.6

A finite state machine (FSM) is implemented using the D flip-flops A and B and logic gates, as shown in the figure below. The four possible states of the FSM are Q

_{A}Q_{B}= 00, 01, 10, and 11.Assume that X_{I}N is held at a logic level throughout the operation of the FSM. When the FSM is initialized to the state Q_{A} Q_{B} = 100 and clocked, after a few clock cycles, it starts cycling through

Questions Asked from Sequential Circuits (Marks 2)

Number in Brackets after Paper Indicates No. of Questions

GATE ECE 2018 (1)
GATE ECE 2017 Set 2 (1)
GATE ECE 2017 Set 1 (2)
GATE ECE 2016 Set 2 (2)
GATE ECE 2015 Set 3 (2)
GATE ECE 2015 Set 2 (1)
GATE ECE 2014 Set 2 (2)
GATE ECE 2014 Set 1 (1)
GATE ECE 2012 (1)
GATE ECE 2011 (2)
GATE ECE 2009 (1)
GATE ECE 2008 (1)
GATE ECE 2007 (2)
GATE ECE 2006 (1)
GATE ECE 2004 (1)
GATE ECE 2003 (1)
GATE ECE 2001 (1)
GATE ECE 2000 (2)
GATE ECE 1999 (1)
GATE ECE 1998 (1)

GATE ECE Subjects

Network Theory

Control Systems

Electronic Devices and VLSI

Analog Circuits

Digital Circuits

Microprocessors

Signals and Systems

Representation of Continuous Time Signal Fourier Series
Fourier Transform
Continuous Time Signal Laplace Transform
Discrete Time Signal Fourier Series Fourier Transform
Discrete Fourier Transform and Fast Fourier Transform
Discrete Time Signal Z Transform
Continuous Time Linear Invariant System
Discrete Time Linear Time Invariant Systems
Transmission of Signal Through Continuous Time LTI Systems
Sampling
Transmission of Signal Through Discrete Time Lti Systems
Miscellaneous

Communications

Electromagnetics

General Aptitude