1
GATE ECE 2004
MCQ (Single Correct Answer)
+2
-0.6
In the modulo-6 ripple counter shown in the figure, the output of the 2-input gate is used to clear the J-K flip-flops. The 2-input gate is GATE ECE 2004 Digital Circuits - Sequential Circuits Question 41 English
A
a NAND gate
B
a NOR gate
C
an OR gate
D
an AND gate
2
GATE ECE 2003
MCQ (Single Correct Answer)
+2
-0.6
A 4 bit ripple counter and a 4 bit synchronous counter are made using flip-flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then
A
R = 10ns, S = 40ns
B
R = 40ns, S = 10ns
C
R = 10ns, S = 30ns
D
R = 30ns, S = 10ns
3
GATE ECE 2001
MCQ (Single Correct Answer)
+2
-0.6
The digital block in the figure is realized using two positive edge triggered D flip-flops. Assume that for t < t0, Q1 = Q2 =0. The circuit in the digital block is given by

GATE ECE 2001 Digital Circuits - Sequential Circuits Question 43 English
A
GATE ECE 2001 Digital Circuits - Sequential Circuits Question 43 English Option 1
B
GATE ECE 2001 Digital Circuits - Sequential Circuits Question 43 English Option 2
C
GATE ECE 2001 Digital Circuits - Sequential Circuits Question 43 English Option 3
D
GATE ECE 2001 Digital Circuits - Sequential Circuits Question 43 English Option 4
4
GATE ECE 2000
MCQ (Single Correct Answer)
+2
-0.6
A sequential circuit using D flip-flop and logic gates is shown in the figure, where X and Y are the inputs and Z is the output. The circuit is GATE ECE 2000 Digital Circuits - Sequential Circuits Question 45 English
A
S–R Flip-Flop with inputs X = R and Y = S
B
S–R Flip-Flop with inputs X = S and Y = R
C
J–K Flip-Flop with inputs X = J and Y = K
D
J–K Flip-Flop with inputs X = K and Y = J
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