The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a

The digital logic shown in the figure satisfies the given state diagram when Q₁ is connected to input A of the XOR gate.

Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?

In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W₁, W₂, W₃ and W₄.

The outputs of the two flip-flops Q₁, Q₂ in the figure shown are initialized to 0, 0. The sequence generated at Q₁ upon application of clock signal is