1
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a GATE ECE 2015 Set 2 Digital Circuits - Sequential Circuits Question 30 English
A
mod - 2 counter
B
mod - 4 counter
C
mod - 5 counter
D
mod - 6 counter
2
GATE ECE 2015 Set 3
MCQ (Single Correct Answer)
+2
-0.6
A three bit pseudo random number generator is shown. Initially the value of output Y = Y2 Y1 Y0 is set to 111. The value of output Y after three clock cycles is GATE ECE 2015 Set 3 Digital Circuits - Sequential Circuits Question 29 English
A
000
B
001
C
010
D
100
3
GATE ECE 2015 Set 3
MCQ (Single Correct Answer)
+2
-0.6
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing GATE ECE 2015 Set 3 Digital Circuits - Sequential Circuits Question 28 English
A
NOR gates to NAND gates
B
inverts to buffers
C
NOR gates to NAND gates and inverters to buffers
D
5 V to ground
4
GATE ECE 2014 Set 1
MCQ (Single Correct Answer)
+2
-0.6
The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to input A of the XOR gate. GATE ECE 2014 Set 1 Digital Circuits - Sequential Circuits Question 35 English

Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?

A
Input A is connected to $${\overline Q _2}$$
B
Input A is connected to $${Q_2}$$
C
Input A is connected to $${\overline Q _1}$$ and S is complemented
D
Input A is connected to $${\overline Q _1}$$
GATE ECE Subjects
EXAM MAP