1
GATE ECE 2017 Set 2
Numerical
+2
-0
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is S0.
If the input sequence is 10101101001101, starting with the left-most bit, then the number of times 'Out' will be 1 is __________.
Your input ____
2
GATE ECE 2016 Set 2
MCQ (Single Correct Answer)
+2
-0.6
For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zero
If the clock (Clk) frequency is 1 GHz, then the counter behaves as a
3
GATE ECE 2016 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The state transition diagram for a finite state machine with states A, B and C, and binary inputs X, Y and Z, is shown in the figure.
Which one of the following statements is correct?
4
GATE ECE 2015 Set 3
MCQ (Single Correct Answer)
+2
-0.6
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing
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Discrete Fourier Transform and Fast Fourier Transform Discrete Time Signal Fourier Series Fourier Transform Continuous Time Signal Laplace Transform Fourier Transform Representation of Continuous Time Signal Fourier Series Transmission of Signal Through Continuous Time LTI Systems Miscellaneous Sampling Continuous Time Linear Invariant System Discrete Time Linear Time Invariant Systems Discrete Time Signal Z Transform Transmission of Signal Through Discrete Time Lti Systems
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