A shift-left Shift Register (SR) and a $D$ flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared and the XOR gate has no propagation delay.

Which of the following options gives the correct binary representation $\left(b_7 b_6 b_5 b_4 b_3 b_2 b_1 b_0\right)$ of the content of the shift register immediately after the $5^{\text {th }}$ clock transition (positive edge)?

A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input $P 0$ is set to logic ' 0 ' and $P 1$ is set to logic ' 1 ' at all times. The timing diagram of the inputs SEL and $S$ are also shown below.

The sequence of output $Y$ from time $T_0$ to $T_3$ is $\qquad$ .

In the circuit shown below, the AND gate has a propagation delay of 1 ns . The edgetriggered flip-flops have a set-up time of 2 ns , a hold-time of 0 ns , and a clock-to-Q delay of 2 ns .

The maximum clock frequency (in MHz , rounded off to the nearest integer) such that there are no setup violations is___________ .

The sequence of states $(Q_1 Q_0)$ of the given synchronous sequential circuit is ________.