1
GATE ECE 2007
MCQ (Single Correct Answer)
+2
-0.6
The following binary values were applied to the X and Y inputs of the NAND latch shown in the figure in the sequence indicated below: X=0, Y=1; X=0, Y=0; X=1, Y=1. The corresponding stable P, Q outputs will be GATE ECE 2007 Digital Circuits - Sequential Circuits Question 29 English
A
P = 1, Q = 0; P = 1, Q = 0; P = 1, Q = 0 or P = 0, Q = 1
B
P = 1, Q = 0; P = 0, Q = 1; or P = 0, Q = 1; P = 0, Q = 1
C
P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 0 or P = 0, Q = 1
D
P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 1
2
GATE ECE 2006
MCQ (Single Correct Answer)
+2
-0.6
Two D-flip-flops, as shown below, are to be connected as a synchronous counter that goes through the following Q1Q0 sequence $$00 \to 01 \to 11 \to 10 \to 00 \to ......$$
The inputs D0 and D1 respectively should be connected as
GATE ECE 2006 Digital Circuits - Sequential Circuits Question 40 English
A
$$\overline {{Q_1}} \,and\,\ {{Q_0}} $$
B
$$\overline {{Q_0}} \,and\,\ {{Q_1}} $$
C
$$\,\overline {{Q_1}} {Q_0}\,and\,\overline {{Q_1}} {Q_0}$$
D
$$\,\overline {{Q_1}} \overline {{Q_0}} \,and\,{Q_1}{Q_0}$$
3
GATE ECE 2004
MCQ (Single Correct Answer)
+2
-0.6
In the modulo-6 ripple counter shown in the figure, the output of the 2-input gate is used to clear the J-K flip-flops. The 2-input gate is GATE ECE 2004 Digital Circuits - Sequential Circuits Question 41 English
A
a NAND gate
B
a NOR gate
C
an OR gate
D
an AND gate
4
GATE ECE 2003
MCQ (Single Correct Answer)
+2
-0.6
A 4 bit ripple counter and a 4 bit synchronous counter are made using flip-flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then
A
R = 10ns, S = 40ns
B
R = 40ns, S = 10ns
C
R = 10ns, S = 30ns
D
R = 30ns, S = 10ns
GATE ECE Subjects
EXAM MAP
Medical
NEETAIIMS
Graduate Aptitude Test in Engineering
GATE CSEGATE ECEGATE EEGATE MEGATE CEGATE PIGATE IN
Civil Services
UPSC Civil Service
Defence
NDA
Staff Selection Commission
SSC CGL Tier I
CBSE
Class 12