1
GATE ECE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence
generated at Q1 upon application of clock signal is
2
GATE ECE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms
W1, W2, W3 and W4.
3
GATE ECE 2012
MCQ (Single Correct Answer)
+2
-0.6
The state transition diagram for the logic circuit shown is
A
B
C
D
4
GATE ECE 2011
MCQ (Single Correct Answer)
+2
-0.6
Two D flip-flops are connected as a synchronous counter that goes through the following QB QA sequence $$00 \to 11 \to 01 \to 10 \to 00 \to ......$$
Questions Asked from Sequential Circuits (Marks 2)
Number in Brackets after Paper Indicates No. of Questions
GATE ECE 2024 (1)
GATE ECE 2023 (1)
GATE ECE 2022 (2)
GATE ECE 2018 (1)
GATE ECE 2017 Set 2 (1)
GATE ECE 2017 Set 1 (2)
GATE ECE 2016 Set 2 (2)
GATE ECE 2015 Set 3 (2)
GATE ECE 2015 Set 2 (1)
GATE ECE 2014 Set 1 (1)
GATE ECE 2014 Set 2 (2)
GATE ECE 2012 (1)
GATE ECE 2011 (2)
GATE ECE 2009 (1)
GATE ECE 2008 (1)
GATE ECE 2007 (2)
GATE ECE 2006 (1)
GATE ECE 2004 (1)
GATE ECE 2003 (1)
GATE ECE 2001 (1)
GATE ECE 2000 (2)
GATE ECE 1999 (1)
GATE ECE 1998 (1)
GATE ECE Subjects
Signals and Systems
Representation of Continuous Time Signal Fourier Series Discrete Time Signal Fourier Series Fourier Transform Discrete Time Signal Z Transform Continuous Time Linear Invariant System Transmission of Signal Through Continuous Time LTI Systems Discrete Time Linear Time Invariant Systems Sampling Continuous Time Signal Laplace Transform Discrete Fourier Transform and Fast Fourier Transform Transmission of Signal Through Discrete Time Lti Systems Miscellaneous Fourier Transform
Network Theory
Control Systems
Digital Circuits
General Aptitude
Electronic Devices and VLSI
Analog Circuits
Engineering Mathematics
Microprocessors
Communications
Electromagnetics