1
GATE ECE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence generated at Q1 upon application of clock signal is GATE ECE 2014 Set 2 Digital Circuits - Sequential Circuits Question 33 English
A
01110
B
01010
C
00110
D
01100
2
GATE ECE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W1, W2, W3 and W4. GATE ECE 2014 Set 2 Digital Circuits - Sequential Circuits Question 34 English 1 GATE ECE 2014 Set 2 Digital Circuits - Sequential Circuits Question 34 English 2
A
W1
B
W2
C
W3
D
W4
3
GATE ECE 2012
MCQ (Single Correct Answer)
+2
-0.6
The state transition diagram for the logic circuit shown is GATE ECE 2012 Digital Circuits - Sequential Circuits Question 36 English
A
GATE ECE 2012 Digital Circuits - Sequential Circuits Question 36 English Option 1
B
GATE ECE 2012 Digital Circuits - Sequential Circuits Question 36 English Option 2
C
GATE ECE 2012 Digital Circuits - Sequential Circuits Question 36 English Option 3
D
GATE ECE 2012 Digital Circuits - Sequential Circuits Question 36 English Option 4
4
GATE ECE 2011
MCQ (Single Correct Answer)
+2
-0.6
The output of a 3-stage Johnson (twisted-ring) counter is fed to a digital-to-analog (D/A) converter as shown in the figure below. Assume all the states of the counter to be unset initially. The waveform which represents the D/A converter output Vo is GATE ECE 2011 Digital Circuits - Sequential Circuits Question 37 English
A
GATE ECE 2011 Digital Circuits - Sequential Circuits Question 37 English Option 1
B
GATE ECE 2011 Digital Circuits - Sequential Circuits Question 37 English Option 2
C
GATE ECE 2011 Digital Circuits - Sequential Circuits Question 37 English Option 3
D
GATE ECE 2011 Digital Circuits - Sequential Circuits Question 37 English Option 4
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