1
GATE ECE 2001
MCQ (Single Correct Answer)
+2
-0.6
The digital block in the figure is realized using two positive edge triggered D flip-flops. Assume that for t < t0, Q1 = Q2 =0. The circuit in the digital block is given by

GATE ECE 2001 Digital Circuits - Sequential Circuits Question 43 English
A
GATE ECE 2001 Digital Circuits - Sequential Circuits Question 43 English Option 1
B
GATE ECE 2001 Digital Circuits - Sequential Circuits Question 43 English Option 2
C
GATE ECE 2001 Digital Circuits - Sequential Circuits Question 43 English Option 3
D
GATE ECE 2001 Digital Circuits - Sequential Circuits Question 43 English Option 4
2
GATE ECE 2000
MCQ (Single Correct Answer)
+2
-0.6
A sequential circuit using D flip-flop and logic gates is shown in the figure, where X and Y are the inputs and Z is the output. The circuit is GATE ECE 2000 Digital Circuits - Sequential Circuits Question 45 English
A
S–R Flip-Flop with inputs X = R and Y = S
B
S–R Flip-Flop with inputs X = S and Y = R
C
J–K Flip-Flop with inputs X = J and Y = K
D
J–K Flip-Flop with inputs X = K and Y = J
3
GATE ECE 2000
MCQ (Single Correct Answer)
+2
-0.6
In the figure, the J and K inputs of all the four Flip-Flops are made high. The frequency of the signal at output Y is GATE ECE 2000 Digital Circuits - Sequential Circuits Question 44 English
A
0.833 KHz
B
1.0 KHz
C
0.91 KHz
D
0.77 KHZ
4
GATE ECE 1999
MCQ (Single Correct Answer)
+2
-0.6
The ripple counter shown in the figure works as a GATE ECE 1999 Digital Circuits - Sequential Circuits Question 46 English
A
mod – 3 up counter
B
mod – 5 up counter
C
mod – 3 down counter
D
mod – 5 down counter
GATE ECE Subjects
EXAM MAP
Medical
NEETAIIMS
Graduate Aptitude Test in Engineering
GATE CSEGATE ECEGATE EEGATE MEGATE CEGATE PIGATE IN
Civil Services
UPSC Civil Service
Defence
NDA
Staff Selection Commission
SSC CGL Tier I
CBSE
Class 12