In a given sequential circuit, initial states are Q$$_1$$ = 1 and Q$$_2$$ = 0. For a clock frequency of 1 MHz, the frequency of signal Q$$_2$$ in kHz, is ___________ (rounded off to the nearest integer).

for the circuit shown, the clock frequency is f₀ and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, ___________.

A state transition diagram with states A, B, and C, and transition probabilities p₁, p₂, ....., p₇ is shown in the figure (e.g., p₁ denotes the probability of transition from state A to B). For this state diagram, select the statements which is/are universally true.

The propagation delay of the exclusive-OR (XOR) gate in the circuit in the figure is 3 ns . The propagation delay of all the flip-flops is assumed to be Zero. The clock (Clk) frequency provided to the circuit is 500 MHz .

Starting from the initial value of the flip-flop outputs $Q_2 Q_1 Q_0=111$ with $D_2=1$, the minimum number of triggering clock edges after which the flip-flop outputs $Q_2 Q_1 Q_0$ becomes 100 (in integer) is $\_\_\_\_$