1
GATE ECE 2022
+1
-0.33

for the circuit shown, the clock frequency is f0 and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, ___________.

A
frequency is f0/4 and duty cycle is 50%
B
frequency is f0/4 and duty cycle is 25%
C
frequency is f0/2 and duty cycle is 50%
D
frequency is f0 and duty cycle is 25%
2
GATE ECE 2022
MCQ (More than One Correct Answer)
+1
-0.33

A state transition diagram with states A, B, and C, and transition probabilities p1, p2, ....., p7 is shown in the figure (e.g., p1 denotes the probability of transition from state A to B). For this state diagram, select the statements which is/are universally true.

A
p2 + p3 = p5 + p6
B
p1 + p3 = p4 + p6
C
p1 + p4 + p7 = 1
D
p2 + p5 + p7 = 1
3
GATE ECE 2018
Numerical
+1
-0.33
A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on for 5 seconds and the RED is turned on for 75 seconds. This traffic light has to be implemented using a finite state machine (FSM). The only input to this FSM is a clock of 5 second period. The minimum number of flip-flops required to implement this FSM is _______.
4
GATE ECE 2017 Set 1
Numerical
+1
-0
Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output latch in percentage is ___________.