for the circuit shown, the clock frequency is f0 and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, ___________.
A
frequency is f0/4 and duty cycle is 50%
B
frequency is f0/4 and duty cycle is 25%
C
frequency is f0/2 and duty cycle is 50%
D
frequency is f0 and duty cycle is 25%
2
GATE ECE 2022
MCQ (More than One Correct Answer)
+2
-0.67
A state transition diagram with states A, B, and C, and transition probabilities p1, p2, .....,
p7 is shown in the figure (e.g., p1 denotes the probability of transition from state A to B). For this state diagram, select the statements which is/are universally true.
A
p2 + p3 = p5 + p6
B
p1 + p3 = p4 + p6
C
p1 + p4 + p7 = 1
D
p2 + p5 + p7 = 1
3
GATE ECE 2018
Numerical
+2
-0.67
In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input
data Din using clock CK. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for
logic LOW levels. The data bit and clock periods are equal and the value of $${{\Delta T} \over {{T_{CK}}}}$$ = 0.15,
where the parameters $$\Delta T$$ and TCK are shown in the figure. Assume that the Flip-Flop and the
XOR gate are ideal.
If the probability of input data bit (Din) transition in each clock period is 0.3, the average
value (in volts, accurate to two decimal places) of the voltage at node X, is _______.
Your input ____
4
GATE ECE 2017 Set 2
Numerical
+2
-0
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is S0.
If the input sequence is 10101101001101, starting with the left-most bit, then the number of times 'Out' will be 1 is __________.
