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1
GATE ECE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W1, W2, W3 and W4. GATE ECE 2014 Set 2 Digital Circuits - Sequential Circuits Question 40 English 1 GATE ECE 2014 Set 2 Digital Circuits - Sequential Circuits Question 40 English 2
A
W1
B
W2
C
W3
D
W4
2
GATE ECE 2014 Set 1
MCQ (Single Correct Answer)
+2
-0.6
The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to input A of the XOR gate. GATE ECE 2014 Set 1 Digital Circuits - Sequential Circuits Question 41 English

Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?

A
Input A is connected to $${\overline Q _2}$$
B
Input A is connected to $${Q_2}$$
C
Input A is connected to $${\overline Q _1}$$ and S is complemented
D
Input A is connected to $${\overline Q _1}$$
3
GATE ECE 2012
MCQ (Single Correct Answer)
+2
-0.6
The state transition diagram for the logic circuit shown is GATE ECE 2012 Digital Circuits - Sequential Circuits Question 42 English
A
GATE ECE 2012 Digital Circuits - Sequential Circuits Question 42 English Option 1
B
GATE ECE 2012 Digital Circuits - Sequential Circuits Question 42 English Option 2
C
GATE ECE 2012 Digital Circuits - Sequential Circuits Question 42 English Option 3
D
GATE ECE 2012 Digital Circuits - Sequential Circuits Question 42 English Option 4
4
GATE ECE 2011
MCQ (Single Correct Answer)
+2
-0.6
Two D flip-flops are connected as a synchronous counter that goes through the following QB QA sequence $$00 \to 11 \to 01 \to 10 \to 00 \to ......$$
A
$${D_A} = {Q_{B,}}\,{D_B} = {Q_A}$$
B
$${D_A} = {\overline Q _A},\,{D_B} = {\overline Q _B}$$
C
$${D_A} = \left( {{Q_A}\,{{\overline Q }_B}\, + {{\overline Q }_A}\,{Q_B}} \right),\,\,{D_B} = {Q_A}$$
D
$${D_A} = \left( {{Q_A}{Q_B} + {{\overline Q }_A}{{\overline Q }_B}} \right),\,\,{D_B} = {\overline Q _B}$$
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