1
GATE ECE 2015 Set 3
MCQ (Single Correct Answer)
+2
-0.6
A three bit pseudo random number generator is shown. Initially the value of output Y = Y2 Y1 Y0 is set to 111. The value of output Y after three clock cycles is
2
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The figure shows a binary counter with synchronous clear input. With the decoding logic shown,
the counter works as a
3
GATE ECE 2014 Set 1
MCQ (Single Correct Answer)
+2
-0.6
The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to
input A of the XOR gate.
Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?
4
GATE ECE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms
W1, W2, W3 and W4.
GATE ECE Subjects
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General Aptitude
Network Theory
Microprocessors
Signals and Systems
Discrete Time Signal Fourier Series Fourier Transform Continuous Time Signal Laplace Transform Fourier Transform Discrete Fourier Transform and Fast Fourier Transform Representation of Continuous Time Signal Fourier Series Discrete Time Linear Time Invariant Systems Transmission of Signal Through Continuous Time LTI Systems Transmission of Signal Through Discrete Time Lti Systems Miscellaneous Continuous Time Linear Invariant System Discrete Time Signal Z Transform Sampling
Electromagnetics
Digital Circuits
Electronic Devices and VLSI
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