1
GATE ECE 2015 Set 3
MCQ (Single Correct Answer)
+2
-0.6
A three bit pseudo random number generator is shown. Initially the value of output Y = Y2 Y1 Y0 is set to 111. The value of output Y after three clock cycles is
2
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The figure shows a binary counter with synchronous clear input. With the decoding logic shown,
the counter works as a
3
GATE ECE 2014 Set 1
MCQ (Single Correct Answer)
+2
-0.6
The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to
input A of the XOR gate.
Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?
4
GATE ECE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence
generated at Q1 upon application of clock signal is
GATE ECE Subjects
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Control Systems
Engineering Mathematics
Analog Circuits
Network Theory
Electromagnetics
Electronic Devices and VLSI
Digital Circuits
Microprocessors
Signals and Systems
Discrete Fourier Transform and Fast Fourier Transform Discrete Time Signal Fourier Series Fourier Transform Continuous Time Signal Laplace Transform Fourier Transform Representation of Continuous Time Signal Fourier Series Transmission of Signal Through Continuous Time LTI Systems Miscellaneous Sampling Continuous Time Linear Invariant System Discrete Time Linear Time Invariant Systems Discrete Time Signal Z Transform Transmission of Signal Through Discrete Time Lti Systems
Communications
General Aptitude