A three bit pseudo random number generator is shown. Initially the value of output Y = Y₂ Y₁ Y₀ is set to 111. The value of output Y after three clock cycles is

An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing

The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a

In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W₁, W₂, W₃ and W₄.