1
GATE ECE 2011
+2
-0.6
Two D flip-flops are connected as a synchronous counter that goes through the following QB QA sequence $$00 \to 11 \to 01 \to 10 \to 00 \to ......$$
A
$${D_A} = {Q_{B,}}\,{D_B} = {Q_A}$$
B
$${D_A} = {\overline Q _A},\,{D_B} = {\overline Q _B}$$
C
$${D_A} = \left( {{Q_A}\,{{\overline Q }_B}\, + {{\overline Q }_A}\,{Q_B}} \right),\,\,{D_B} = {Q_A}$$
D
$${D_A} = \left( {{Q_A}{Q_B} + {{\overline Q }_A}{{\overline Q }_B}} \right),\,\,{D_B} = {\overline Q _B}$$
2
GATE ECE 2009
+2
-0.6
What are the counting states (Q1, Q2) for the counter shown in the figure below? A
11, 10, 00, 11, 10,......
B
01,1011,00,01........,
C
00,11,01,10,00........
D
01,10,00,01,10........
3
GATE ECE 2008
+2
-0.6
For each of the positive edge-triggered J-K flip flop used in the following future, the propagation delay is $$\Delta$$T Which of the following waveforms correctly represents the output at Q1?

A B C D 4
GATE ECE 2007
+2
-0.6
For the circuit shown, the counter state (Q1 Q0) follows the sequence A
00,01,10,11,00......
B
00,01,10,00,01.......
C
00,01,11,00,01.....
D
00,10,11,00,10......
GATE ECE Subjects
Signals and Systems
Network Theory
Control Systems
Digital Circuits
General Aptitude
Electronic Devices and VLSI
Analog Circuits
Engineering Mathematics
Microprocessors
Communications
Electromagnetics
EXAM MAP
Joint Entrance Examination