For the circuit shown, the counter state (Q₁ Q₀) follows the sequence

Two D-flip-flops, as shown below, are to be connected as a synchronous counter that goes through the following Q₁Q₀ sequence $$00 \to 01 \to 11 \to 10 \to 00 \to ......$$
The inputs D₀ and D₁ respectively should be connected as

In the modulo-6 ripple counter shown in the figure, the output of the 2-input gate is used to clear the J-K flip-flops. The 2-input gate is

A 4 bit ripple counter and a 4 bit synchronous counter are made using flip-flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then