1
GATE ECE 2007
MCQ (Single Correct Answer)
+2
-0.6
For the circuit shown, the counter state (Q1 Q0) follows the sequence
A
00,01,10,11,00......
B
00,01,10,00,01.......
C
00,01,11,00,01.....
D
00,10,11,00,10......
2
GATE ECE 2007
MCQ (Single Correct Answer)
+2
-0.6
The following binary values were applied to the X and Y inputs of the NAND latch shown in the figure in the sequence indicated below: X=0, Y=1; X=0, Y=0; X=1, Y=1. The corresponding stable P, Q outputs will be
A
P = 1, Q = 0; P = 1, Q = 0; P = 1, Q = 0 or P = 0, Q = 1
B
P = 1, Q = 0; P = 0, Q = 1; or P = 0, Q = 1; P = 0, Q = 1
C
P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 0 or P = 0, Q = 1
D
P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 1
3
GATE ECE 2006
MCQ (Single Correct Answer)
+2
-0.6
Two D-flip-flops, as shown below, are to be connected as a synchronous counter that goes through the following Q1Q0 sequence $$00 \to 01 \to 11 \to 10 \to 00 \to ......$$
The inputs D0 and D1 respectively should be connected as
A
$$\overline {{Q_1}} \,and\,\ {{Q_0}}$$
B
$$\overline {{Q_0}} \,and\,\ {{Q_1}}$$
C
$$\,\overline {{Q_1}} {Q_0}\,and\,\overline {{Q_1}} {Q_0}$$
D
$$\,\overline {{Q_1}} \overline {{Q_0}} \,and\,{Q_1}{Q_0}$$
4
GATE ECE 2004
MCQ (Single Correct Answer)
+2
-0.6
In the modulo-6 ripple counter shown in the figure, the output of the 2-input gate is used to clear the J-K flip-flops. The 2-input gate is
A
a NAND gate
B
a NOR gate
C
an OR gate
D
an AND gate
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