GATE ECE 2007 | Sequential Circuits Question 32 | Digital Circuits

GATE ECE 2007

MCQ (Single Correct Answer)

-0.6

For the circuit shown, the counter state (Q₁ Q₀) follows the sequence GATE ECE 2007 Digital Circuits - Sequential Circuits Question 35 English

00,01,10,11,00......

00,01,10,00,01.......

00,01,11,00,01.....

00,10,11,00,10......

GATE ECE 2007

MCQ (Single Correct Answer)

-0.6

The following binary values were applied to the X and Y inputs of the NAND latch shown in the figure in the sequence indicated below: X=0, Y=1; X=0, Y=0; X=1, Y=1. The corresponding stable P, Q outputs will be GATE ECE 2007 Digital Circuits - Sequential Circuits Question 26 English

GATE ECE 2007 Digital Circuits - Sequential Circuits Question 26 English

P = 1, Q = 0; P = 1, Q = 0; P = 1, Q = 0 or P = 0, Q = 1

P = 1, Q = 0; P = 0, Q = 1; or P = 0, Q = 1; P = 0, Q = 1

P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 0 or P = 0, Q = 1

P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 1

GATE ECE 2006

MCQ (Single Correct Answer)

-0.6

Two D-flip-flops, as shown below, are to be connected as a synchronous counter that goes through the following Q₁Q₀ sequence $$00 \to 01 \to 11 \to 10 \to 00 \to ......$$
The inputs D₀ and D₁ respectively should be connected as
GATE ECE 2006 Digital Circuits - Sequential Circuits Question 37 English

GATE ECE 2006 Digital Circuits - Sequential Circuits Question 37 English

$$\overline {{Q_1}} \,and\,\ {{Q_0}} $$

$$\overline {{Q_0}} \,and\,\ {{Q_1}} $$

$$\,\overline {{Q_1}} {Q_0}\,and\,\overline {{Q_1}} {Q_0}$$

$$\,\overline {{Q_1}} \overline {{Q_0}} \,and\,{Q_1}{Q_0}$$

GATE ECE 2004

MCQ (Single Correct Answer)

-0.6

In the modulo-6 ripple counter shown in the figure, the output of the 2-input gate is used to clear the J-K flip-flops. The 2-input gate is GATE ECE 2004 Digital Circuits - Sequential Circuits Question 38 English