A finite state machine (FSM) is implemented using the D flip-flops A and B and logic gates, as shown in the figure below. The four possible states of the FSM are Q_A Q_B = 00, 01, 10, and 11.

Assume that X_IN is held at a logic level throughout the operation of the FSM. When the FSM is initialized to the state Q_A Q_B = 100 and clocked, after a few clock cycles, it starts cycling through

The state transition diagram for a finite state machine with states A, B and C, and binary inputs X, Y and Z, is shown in the figure.

Which one of the following statements is correct?

For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zero

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a

A three bit pseudo random number generator is shown. Initially the value of output Y = Y₂ Y₁ Y₀ is set to 111. The value of output Y after three clock cycles is