The state transition diagram for a finite state machine with states A, B and C, and binary inputs X, Y and Z, is shown in the figure.

Which one of the following statements is correct?

For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zero

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a

The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a

A three bit pseudo random number generator is shown. Initially the value of output Y = Y₂ Y₁ Y₀ is set to 111. The value of output Y after three clock cycles is