A state transition diagram with states A, B, and C, and transition probabilities p₁, p₂, ....., p₇ is shown in the figure (e.g., p₁ denotes the probability of transition from state A to B). For this state diagram, select the statements which is/are universally true.

The propagation delay of the exclusive-OR (XOR) gate in the circuit in the figure is 3 ns . The propagation delay of all the flip-flops is assumed to be Zero. The clock (Clk) frequency provided to the circuit is 500 MHz .

Starting from the initial value of the flip-flop outputs $Q_2 Q_1 Q_0=111$ with $D_2=1$, the minimum number of triggering clock edges after which the flip-flop outputs $Q_2 Q_1 Q_0$ becomes 100 (in integer) is $\_\_\_\_$

For the components in the sequential circuit shown below, $t_{p d}$ is the propagation delay, $t_{\text {secup }}$ is the setup time and $t_{\text {hold }}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is $\_\_\_\_$ MHz.

The state diagram of a sequence detector is shown below. State $S_0$ is the initial state of the sequence detector. If the output is 1 , then