In the circuit shown below, the AND gate has a propagation delay of 1 ns . The edgetriggered flip-flops have a set-up time of 2 ns , a hold-time of 0 ns , and a clock-to-Q delay of 2 ns .

The maximum clock frequency (in MHz , rounded off to the nearest integer) such that there are no setup violations is___________ .

The sequence of states $(Q_1 Q_0)$ of the given synchronous sequential circuit is ________.

In a given sequential circuit, initial states are Q$$_1$$ = 1 and Q$$_2$$ = 0. For a clock frequency of 1 MHz, the frequency of signal Q$$_2$$ in kHz, is ___________ (rounded off to the nearest integer).

for the circuit shown, the clock frequency is f₀ and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, ___________.