1
GATE ECE 2012
+2
-0.6
In the three dimensional view of a silicon n-channel MOS transistor shown below, $$\delta = 20$$ nm. The transistor is of width 1 $$\mu m$$. The depletion width formed at every p-n junction is 10 nm. The relative permittivities of Si and SiO2, respectively, are 11.7 and 3.9, and $${\varepsilon _0}$$ = 8.9 $$\times {10^{ - 12}}$$ F/m.

The gate-source overlap capacitance is approximately

A
0.7 fF
B
0.7 pF
C
0.35 fF
D
0.24 pF
2
GATE ECE 2012
+2
-0.6
The source of a silicon (ni = 1010 per cm3) n - channel MOS transistor has an aewa of 1 sq $$\mu m$$ and a depth of 1 $$\mu m$$ . If the dopant density in the source is 1019/cm3, the number of holes in the source region with the above volume is approximately
A
107
B
100
C
10
D
0
3
GATE ECE 2012
+2
-0.6
In the three dimensional view of a silicon n-channel MOS transistor shown below, $$\delta = 20$$ nm. The transistor is of width 1 $$\mu m$$. The depletion width formed at every p-n junction is 10 nm. The relative permittivities of Si and SiO2, respectively, are 11.7 and 3.9, and $${\varepsilon _0}$$ = 8.9 $$\times {10^{ - 12}}$$ F/m.

The source-body junction capacitance is approximately

A
2 fF
B
7 fF
C
2 pF
D
7 pF
4
GATE ECE 2012
+2
-0.6
In the CMOS circuit shown, electron and hole mobilities are equal, and M1 and M2 are equally sized. The device M1 is in the linear region if
A
V in < 1.875 V
B
1.875 V < V in < 3.125 V
C
V in > 3.125 V
D
0 < V in < 5 V
EXAM MAP
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