In the three dimensional view of a silicon n-channel MOS transistor shown below, $$\delta = 20$$ nm. The transistor is of width 1 $$\mu m$$. The depletion width formed at every p-n junction is 10 nm. The relative permittivities of Si and SiO₂, respectively, are 11.7 and 3.9, and $${\varepsilon _0}$$ = 8.9 $$ \times {10^{ - 12}}$$ F/m.

The gate-source overlap capacitance is approximately

In the three dimensional view of a silicon n-channel MOS transistor shown below, $$\delta = 20$$ nm. The transistor is of width 1 $$\mu m$$. The depletion width formed at every p-n junction is 10 nm. The relative permittivities of Si and SiO₂, respectively, are 11.7 and 3.9, and $${\varepsilon _0}$$ = 8.9 $$ \times {10^{ - 12}}$$ F/m.

The source-body junction capacitance is approximately

In the CMOS circuit shown, electron and hole mobilities are equal, and M₁ and M₂ are equally sized. The device M₁ is in the linear region if

Consider the CMOS circuit shown, where the gate voltage of the n-MOSFET is increased from zero, while the gate voltage of the p-MOSFET is kept constant at 3 V. Assume that, for both transistors, the magnitude of the threshold voltage is 1 V and the product of the transconductance parameter and the $$\left(\frac WL\right)$$ ratio, i.e. the quantity $$\mu C_{ox}\left(\frac WL\right)$$ , is 1 mAV^-2.
Estimate the output voltage V₀ for V_G =1.5 V. [Hints: Use the appropriate current-voltage equation for each MOSFET, based on the answer]