Consider an n-channel MOSFET having width W, length L, electron mobility in the channel $$\mu_n$$ and oxide capacitance per unit area $$C_{ox}$$. If gate-to-source voltage V_GS=0.7 V, drain-to source voltage V_DS=0.1V, $$\left(\mu_nC_{ox}\right)\;=\;100\;\mu A/V^2$$, threshold voltage V_TH=0.3 V and (W/L) = 50, then the transconductance g_m (in mA/V) is ___________.

For the circuit shown in the figure, P and Q are the inputs and Y is the output. The logic implemented by the circuit is

The figure shows the band diagram of a Metal Oxide Semiconductor (MOS). The surface region of this MOS is in

A long-channel NMOS transistor is biased in the linear region with V_DS = 50 mV and is used as a resistance. Which one of the following statements is NOT correct?