1
GATE ECE 2017 Set 2
Numerical
+1
-0
Consider an n-channel MOSFET having width W, length L, electron mobility in the channel $$\mu_n$$ and oxide capacitance per unit area $$C_{ox}$$. If gate-to-source voltage VGS=0.7 V, drain-to source voltage VDS=0.1V, $$\left(\mu_nC_{ox}\right)\;=\;100\;\mu A/V^2$$, threshold voltage VTH=0.3 V and (W/L) = 50, then the transconductance gm (in mA/V) is ___________.
Your input ____
2
GATE ECE 2017 Set 2
MCQ (Single Correct Answer)
+1
-0.3
For the circuit shown in the figure, P and Q are the inputs and Y is the output. GATE ECE 2017 Set 2 Electronic Devices and VLSI - IC Basics and MOSFET Question 40 English The logic implemented by the circuit is
A
XNOR
B
XOR
C
NOR
D
OR
3
GATE ECE 2016 Set 3
MCQ (Single Correct Answer)
+1
-0.3
The figure shows the band diagram of a Metal Oxide Semiconductor (MOS). The surface region of this MOS is in GATE ECE 2016 Set 3 Electronic Devices and VLSI - IC Basics and MOSFET Question 43 English
A
inversion
B
accumulation
C
depletion
D
flat band
4
GATE ECE 2016 Set 2
MCQ (Single Correct Answer)
+1
-0.3
A long-channel NMOS transistor is biased in the linear region with VDS = 50 mV and is used as a resistance. Which one of the following statements is NOT correct?
A
If the device width W is increased, the resistance decreases.
B
If the threshold voltage is reduced, the resistance decreases.
C
If the device length L is increased, the resistance increases.
D
If VGS is increased, the resistance increases.
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