1
GATE ECE 2016 Set 2
+1
-0.3
Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for worst case charge and discharge times for driving a load capacitor C. This design is to be converted to that of a NOR circuit in the same technology, so that its worst case charge and discharge times while driving the same capacitor are similar. The channel lengths of all transistors are to be kept unchanged. Which one of the following statements is correct?
A
Widths of PMOS transistors should be doubled, while widths of NMOS transistors should be halved.
B
Widths of PMOS transistors should be doubled, while widths of NMOS transistors should not be changed.
C
Widths of PMOS transistors should be halved, while widths of NMOS transistors should not be changed.
D
Widths of PMOS transistors should be unchanged, while widths of NMOS transistors should be halved.
2
GATE ECE 2016 Set 3
+1
-0.3
The figure shows the band diagram of a Metal Oxide Semiconductor (MOS). The surface region of this MOS is in
A
inversion
B
accumulation
C
depletion
D
flat band
3
GATE ECE 2016 Set 1
+1
-0.3
Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET):

P: As channel length reduces, OFF-state current increases.
Q:As channel length reduces, output resistance increases.
R: As channel length reduces, threshold voltage remains constant.
S: As channel length reduces, ON current increases.

Which of the above statements are INCORRECT?
A
P and Q
B
P and S
C
Q and R
D
R and S
4
GATE ECE 2016 Set 1
+1
-0.3
What is the voltage Vout in the following circuit?
A
0 V
B
$$\left(\left|V_T\;of\;PMOS\right|\;+\;V_T\;of\;NMOS\right)/2$$
C
Switching threshold of inverter
D
VDD
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