1
GATE ECE 2016 Set 2
MCQ (Single Correct Answer)
+1
-0.3
Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for
worst case charge and discharge times for driving a load capacitor C. This design is to be
converted to that of a NOR circuit in the same technology, so that its worst case charge and
discharge times while driving the same capacitor are similar. The channel lengths of all
transistors are to be kept unchanged. Which one of the following statements is correct?


2
GATE ECE 2016 Set 2
MCQ (Single Correct Answer)
+1
-0.3
A long-channel NMOS transistor is biased in the linear region with VDS = 50 mV and is used
as a resistance. Which one of the following statements is NOT correct?
3
GATE ECE 2016 Set 1
MCQ (Single Correct Answer)
+1
-0.3
Consider the following statements for a metal oxide semiconductor field effect transistor
(MOSFET):
P: As channel length reduces, OFF-state current increases.
Q:As channel length reduces, output resistance increases.
R: As channel length reduces, threshold voltage remains constant.
S: As channel length reduces, ON current increases.
4
GATE ECE 2016 Set 1
MCQ (Single Correct Answer)
+1
-0.3
What is the voltage Vout in the following circuit?
GATE ECE Subjects
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General Aptitude
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Discrete Time Signal Fourier Series Fourier Transform Continuous Time Signal Laplace Transform Fourier Transform Discrete Fourier Transform and Fast Fourier Transform Representation of Continuous Time Signal Fourier Series Discrete Time Linear Time Invariant Systems Transmission of Signal Through Continuous Time LTI Systems Transmission of Signal Through Discrete Time Lti Systems Miscellaneous Continuous Time Linear Invariant System Discrete Time Signal Z Transform Sampling
Electromagnetics
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Electronic Devices and VLSI
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