1
GATE ECE 1998
MCQ (Single Correct Answer)
+1
-0.3
The noise margin of a TTL gate is about
A
0.2V
B
0.4V
C
0.6V
D
0.8V
2
GATE ECE 1998
MCQ (Single Correct Answer)
+1
-0.3
The threshold voltage for each transistor in Fig.2.5, is 2V. For this circuit to work as an inverter, Vi must take the values GATE ECE 1998 Digital Circuits - Logic Families Question 18 English
A
-5 V and 0 V
B
-5 V and 5 V
C
-0 V and 3 V
D
3 V and 5 V
3
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
In standard TTL the 'totem pole' stage refers to
A
the multi-emitteer input stage
B
the phase splitter
C
the output buffer
D
open collector output stage
4
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
The inverter 74AL SO4 has the following specifications:
$${I_{OH}}{\,_{\max \,}} = \, - $$ 0.4mA, $${I_{OL}}$$ max = 8mA, $${I_{IH}}$$ max = $$\mu $$A , $${I_{IL\,}}_{\max \,}$$=0.1mA. The fan out based on the above will be
A
10
B
20
C
60
D
100
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