1
GATE ECE 2005
MCQ (Single Correct Answer)
+1
-0.3
Both transistors T1 and T2 in figure have a threshold voltage of 1 Volt. The device parameters $${K_1}$$ and $${K_2}$$ of $${T_1}$$ and $${T_2}$$ are, respectively, 36 µA/ $${V^2}$$ and and 9$$9\,A/{V^2}$$. The output voltage $${V_0}$$ IS GATE ECE 2005 Digital Circuits - Logic Families Question 10 English
A
1V
B
2V
C
3V
D
4V
2
GATE ECE 2004
MCQ (Single Correct Answer)
+1
-0.3
Figure shows the internal schematic of a TTL AND-OR-Invert (AOI) gate. For the inputs shown in Figure, the output Y is GATE ECE 2004 Digital Circuits - Logic Families Question 13 English
A
0
B
1V
C
AB
D
$$\overline {AB} $$
3
GATE ECE 2003
MCQ (Single Correct Answer)
+1
-0.3
The output of the 74 series of TTL gates is taken from a BJT in
A
Totem pole and common collector configuration
B
either totem pole or open collector configuration
C
common base configuration
D
common collector configuration
4
GATE ECE 1999
MCQ (Single Correct Answer)
+1
-0.3
Commercially available ECL gates use two ground lines and one negative supply in order to
A
reduce power dissipation
B
increase fan-out
C
reduce loading effect
D
eliminate the effect of power line glitches or the biasing circuit.
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