The figure shows the circuit of a gate in the Resistor Transistor Logic (RTL) family. The circuit represents a

The CMOS equivalent of the following n MOS gate (figure) is ________ (draw the circuit ).

In figure, the Boolean expression for the output in terms of inputs A, B and C when the clock ‘CK’ is high, is given by _______.

A logic family has threshold voltage $${V_T}$$= 2V, minimum guaranteed output high voltage $${V_{OH}}$$= 4V, minimum accepted input high voltage $${V_{IH}}$$ = 3V, maximum guaranteed output low voltage $${V_{OL}}$$ = 1V, and maximum accepted input low voltage N $${V_{IL}}$$ =1.5V. Its noise margin is