1
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
For the NMOS logic gate shown in figure, the logic function implemented is GATE ECE 1997 Digital Circuits - Logic Families Question 20 English
A
$$\overline {ABCDE} $$
B
$$(AB + \overline C ).(\overline {D + E} )$$
C
$$\overline {A.(B + C) + D.E} $$
D
$$(\overline {A + B} ).C + \overline D .\overline E $$
2
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because
A
the driver transistor has a larger threshold voltage than the load transistor.
B
the driver transistor has larger leakage currents compared to the load transistor.
C
the load transistor has a smaller W/L ratio compared to the driver transistor
D
none of the above
3
GATE ECE 1992
MCQ (Single Correct Answer)
+1
-0.3
The figure shows the circuit of a gate in the Resistor Transistor Logic (RTL) family. The circuit represents a GATE ECE 1992 Digital Circuits - Logic Families Question 23 English
A
NAND
B
AND
C
NOR
D
OR
4
GATE ECE 1991
Fill in the Blanks
+1
-0
The CMOS equivalent of the following n MOS gate (figure) is ________ (draw the circuit ). GATE ECE 1991 Digital Circuits - Logic Families Question 25 English
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