1
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
For the NMOS logic gate shown in figure, the logic function implemented is

2
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because
3
GATE ECE 1992
MCQ (Single Correct Answer)
+1
-0.3
The figure shows the circuit of a gate in the Resistor Transistor Logic (RTL) family. The circuit represents a

4
GATE ECE 1991
Fill in the Blanks
+1
-0
The CMOS equivalent of the following n MOS gate (figure) is ________ (draw the circuit ).


Questions Asked from Logic Families (Marks 1)
Number in Brackets after Paper Indicates No. of Questions
GATE ECE Subjects
Signals and Systems
Representation of Continuous Time Signal Fourier Series
Discrete Time Signal Fourier Series Fourier Transform
Discrete Time Signal Z Transform
Continuous Time Linear Invariant System
Transmission of Signal Through Continuous Time LTI Systems
Discrete Time Linear Time Invariant Systems
Sampling
Continuous Time Signal Laplace Transform
Discrete Fourier Transform and Fast Fourier Transform
Transmission of Signal Through Discrete Time Lti Systems
Miscellaneous
Fourier Transform
Network Theory
Control Systems
Digital Circuits
General Aptitude
Electronic Devices and VLSI
Analog Circuits
Engineering Mathematics
Microprocessors
Communications
Electromagnetics