1
GATE ECE 2022
MCQ (More than One Correct Answer)
+1
-0.33

Select the correct statement(s) regarding CMOS implementation of NOT gates.

A
Noise Margin High (NMH) is always equal to the Noise Margin Low (NML), irrespective of the sizing of transistors.
B
Dynamic power consumption during switching is zero.
C
For a logical high input under steady state, the nMOSFET is in the linear regime of operation.
D
Mobility of electrons never influences the switching speed of the NOT gate.
2
GATE ECE 2014 Set 4
MCQ (Single Correct Answer)
+1
-0.3
The output (Y) of the circuit shown in the figure is GATE ECE 2014 Set 4 Digital Circuits - Logic Families Question 9 English
A
$$\overline A + \overline B + \overline C $$
B
$$A + \overline B \,\overline {.\,C} + A.\,\overline C $$
C
$$\overline A + B + \overline C $$
D
$$A.B.\overline C $$
3
GATE ECE 2009
MCQ (Single Correct Answer)
+1
-0.3
The full forms of the abbreviations TTL and COMS in reference to logic families are
A
Triple Transistor Logic and chip metal oxide semiconductor.
B
Tri-state Transistor Logic and chip metal oxide semiconductor.
C
Transistor Transistor Logic and chip metal oxide semiconductor.
D
Tri-state Transistor Transistor Logic and complementary metal oxide oxide silicon.
4
GATE ECE 2005
MCQ (Single Correct Answer)
+1
-0.3
The transistors used in a portion of the TTL gate shown in figure have β=100. the base-emitter voltage of is 0.7V for a transistor in active region and 0.75V for a transistor in saturation . If the sink current I=1mA and the output is at logic 0, then the current $${I_R}$$ I will be equal to GATE ECE 2005 Digital Circuits - Logic Families Question 12 English
A
0.65 mA
B
0.70 mA
C
0.75 mA
D
1.00 mA
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