1
GATE ECE 2016 Set 1
MCQ (Single Correct Answer)
+2
-0.6
The functionality implemented by the circuit below is
![GATE ECE 2016 Set 1 Digital Circuits - Combinational Circuits Question 21 English](https://gateclass.cdn.examgoal.net/examside/questions/b228ff11293d1189c067fedc3d3f634960fe9e44d88b5392b2d150322307fa77.jpg)
![GATE ECE 2016 Set 1 Digital Circuits - Combinational Circuits Question 21 English](https://gateclass.cdn.examgoal.net/examside/questions/b228ff11293d1189c067fedc3d3f634960fe9e44d88b5392b2d150322307fa77.jpg)
2
GATE ECE 2016 Set 1
MCQ (Single Correct Answer)
+2
-0.6
Identify the circuit below.
![GATE ECE 2016 Set 1 Digital Circuits - Combinational Circuits Question 22 English](https://gateclass.cdn.examgoal.net/examside/questions/12ceefa47cf6435992eac93f1e35204a2e9950c08dfbb9075184a1832cc7e75b.jpg)
3
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
A 1-to-8 demultiplexer with data input D$$_{in}$$ , address inputs S$$_{0}$$, S$$_{1}$$, S$$_{2}$$ (with S$$_{0}$$ as the LSB) and $${\overline Y _0}$$ to $${\overline Y _7}$$
as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input $$\overline E $$ and address inputs A$$_{0}$$ and A$$_{1}$$) as shown in the figure. $${D_{in}}$$, S$$_{0}$$, S$$_{1}$$and S$$_{2}$$ are to be
connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P,
Q, R, and S terminals should be
![GATE ECE 2015 Set 2 Digital Circuits - Combinational Circuits Question 23 English](https://gateclass.cdn.examgoal.net/examside/questions/03b90d694e35b87643e557c883336838a37e68604f60716fb8d6a9df83cee518.jpg)
![GATE ECE 2015 Set 2 Digital Circuits - Combinational Circuits Question 23 English](https://gateclass.cdn.examgoal.net/examside/questions/03b90d694e35b87643e557c883336838a37e68604f60716fb8d6a9df83cee518.jpg)
4
GATE ECE 2014 Set 4
Numerical
+2
-0
A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure.
The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is
15 ns. The worst case delay (in ns) of this 16-bit adder will be_______________.
![GATE ECE 2014 Set 4 Digital Circuits - Combinational Circuits Question 24 English](https://gateclass.cdn.examgoal.net/examside/questions/a9ed07fdb7ac219323cd4266d931cda815a5e3bd56ceea4950a5bac8b9f75e41.jpg)
![GATE ECE 2014 Set 4 Digital Circuits - Combinational Circuits Question 24 English](https://gateclass.cdn.examgoal.net/examside/questions/a9ed07fdb7ac219323cd4266d931cda815a5e3bd56ceea4950a5bac8b9f75e41.jpg)
Your input ____
Questions Asked from Combinational Circuits (Marks 2)
Number in Brackets after Paper Indicates No. of Questions
GATE ECE 2024 (2)
GATE ECE 2018 (1)
GATE ECE 2017 Set 2 (2)
GATE ECE 2016 Set 3 (1)
GATE ECE 2016 Set 1 (2)
GATE ECE 2015 Set 2 (1)
GATE ECE 2014 Set 4 (2)
GATE ECE 2014 Set 3 (2)
GATE ECE 2010 (1)
GATE ECE 2009 (1)
GATE ECE 2008 (1)
GATE ECE 2007 (1)
GATE ECE 2004 (1)
GATE ECE 2003 (2)
GATE ECE 2001 (1)
GATE ECE 1999 (1)
GATE ECE Subjects
Signals and Systems
Representation of Continuous Time Signal Fourier Series Discrete Time Signal Fourier Series Fourier Transform Discrete Time Signal Z Transform Continuous Time Linear Invariant System Transmission of Signal Through Continuous Time LTI Systems Discrete Time Linear Time Invariant Systems Sampling Continuous Time Signal Laplace Transform Discrete Fourier Transform and Fast Fourier Transform Transmission of Signal Through Discrete Time Lti Systems Miscellaneous Fourier Transform
Network Theory
Control Systems
Digital Circuits
General Aptitude
Electronic Devices and VLSI
Analog Circuits
Engineering Mathematics
Microprocessors
Communications
Electromagnetics