1
GATE ECE 2016 Set 1
MCQ (Single Correct Answer)
+2
-0.6
The functionality implemented by the circuit below is GATE ECE 2016 Set 1 Digital Circuits - Combinational Circuits Question 18 English
A
2-to-1 multiplexer
B
4-to-1 multiplexer
C
7-to-1 multiplexer
D
6-to-1 multiplexer
2
GATE ECE 2016 Set 1
MCQ (Single Correct Answer)
+2
-0.6
Identify the circuit below. GATE ECE 2016 Set 1 Digital Circuits - Combinational Circuits Question 19 English
A
Binary to Gray code converter
B
Binary to XS3 converter
C
Gray to Binary converter
D
XS3 to Binary converter
3
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
A 1-to-8 demultiplexer with data input D$$_{in}$$ , address inputs S$$_{0}$$, S$$_{1}$$, S$$_{2}$$ (with S$$_{0}$$ as the LSB) and $${\overline Y _0}$$ to $${\overline Y _7}$$ as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input $$\overline E $$ and address inputs A$$_{0}$$ and A$$_{1}$$) as shown in the figure. $${D_{in}}$$, S$$_{0}$$, S$$_{1}$$and S$$_{2}$$ are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be GATE ECE 2015 Set 2 Digital Circuits - Combinational Circuits Question 20 English
A
$${S_2},\,{D_{in}},\,{S_0},\,{S_1}$$
B
$${S_1},\,{D_{in}},\,{S_0},\,{S_2}$$
C
$${D_{in}},\,{S_0},\,\,{S_1}\,{S_2}$$
D
$${D_{in}},\,{S_2},\,{S_0},\,{S_1}$$
4
GATE ECE 2014 Set 4
Numerical
+2
-0
A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be_______________. GATE ECE 2014 Set 4 Digital Circuits - Combinational Circuits Question 21 English
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