1
GATE ECE 2014 Set 4
Numerical
+2
-0
A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure.
The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is
15 ns. The worst case delay (in ns) of this 16-bit adder will be_______________.
Your input ____
2
GATE ECE 2014 Set 4
MCQ (Single Correct Answer)
+2
-0.6
An 8-to-1 multiplexer is used to implement a logical function Y as shown in the figure. The output Y is given by
3
GATE ECE 2010
MCQ (Single Correct Answer)
+2
-0.6
The Boolean function realized by the logic circuit shown is
4
GATE ECE 2009
MCQ (Single Correct Answer)
+2
-0.6
What are the minimum number of 2-to 1 multiplexers required to generate a 2-input AND gate and a 2-input EX-OR gate?
GATE ECE Subjects
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General Aptitude
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Discrete Fourier Transform and Fast Fourier Transform Discrete Time Signal Fourier Series Fourier Transform Continuous Time Signal Laplace Transform Fourier Transform Representation of Continuous Time Signal Fourier Series Transmission of Signal Through Continuous Time LTI Systems Miscellaneous Sampling Continuous Time Linear Invariant System Discrete Time Linear Time Invariant Systems Discrete Time Signal Z Transform Transmission of Signal Through Discrete Time Lti Systems
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